Introduction

For more than 40 years, integrated-circuit device density has experienced exponential growth (a phenomenon known as Moore’s law [1]). As traditional CMOS transistor scaling limits are being approached, there are many technologies that are being considered to supplant or integrate with CMOS to continue scaling into the terascale (1012 devices/cm2) regime. This chapter reviews some of these future device technologies.

The scope of this chapter is confined to devices that could be direct replacements for (or complements to) to existing CMOS transistors and which are not presently mature enough for volume manufacturing (e.g., high electron mobility transistors and GaN were included, but not fully depleted silicon-on-insulator, or FinFET, devices). The use of other materials in conventional transistor structures is covered only for devices in which the basic operation of the device is vastly different than that of standard silicon-based MOS transistors (e.g., GaN-channel devices were included, but not III-V-channel MOS or germanium-channel MOS devices). Furthermore, the scope is restricted to devices based on charge transport. Although spin transport devices are of increasing interest, they would require a radical shift from the existing circuit architecture used today for CMOS technology.

Additionally, some devices were not included in this review due to other wellrecognized limitations. For example, junction gate field effect transistors (JFETs) were not included, since the primary motivation of this work is extreme scalability of devices. Similarly, although organic semiconductor devices have excellent cost scaling per unit area, their potential for miniaturization and high-performance operation is poor. Carbon-based nanoelectronic structures, such as nanotubes and graphene–nanoribbon devices, also were not included due to current concerns about their manufacturability at the terascale level of integration.

Steady miniaturization of CMOS (complementary metal–oxide–semiconductor) transistors – the predominant type of electrical switches used in digital integrated circuit “chips” – has yielded continual improvements in the performance and cost-per-function of electronic devices over the past four decades. This relentless miniaturization has resulted in ubiquitous information technology with dramatic global impact on virtually every aspect of life in modern society.

CMOS technology is reaching a state of maturity wherein continued transistor scaling will not be as straightforward in the future as it has been in the past. This is already apparent from the slowdown in certain aspects of scaling (e.g., chip supply voltage scaling, transistor off-state leakage current scaling, and so on). Clearly, improved switch designs will be needed to sustain the growth of the electronics industry beyond the next decade. A wide variety of alternative switch designs are being discussed in the research community, many of which use operating principles dramatically different from those of conventional CMOS transistors. Unfortunately, papers published by the research community in rapidly developing fields are rarely tutorial. Thus, much of this important new information is not readily comprehensible to the mainstream electronics community.

To help address this communication gap, we approached recognized experts in the research community with requests to create tutorial essays in their area of speciality. This book organizes these essays into sections, beginning with background information on the power–performance trade-off (motivating steep sub-threshold swing devices), continuing with tunneling-based devices, alternative field effect devices, and spin-based (magnetic) devices. It closes by reviewing the challenges of interconnects for these evolving new switch designs.

Magnetic computing defined

Magnetic computing – in the broadest sense – is about using magnetic signals (nanomagnets, domain walls) to represent and process information. Nowadays, when “information processing” and “electronics” is synonymous, this concept sounds rather exotic. However, before the triumphant era of CMOS logic devices, non-charge based computers were serious candidates for information processing – for example, ingenious magnetic computing circuits were invented by R. J. Spain [1–3]. It was Cowburn [4] who first realized that the properties of nanoscale, single-domain magnets – which are very different from large, multi-domain magnets – are well suited for digital computing.

This chapter deals with one approach to magnetic computing, nanomagnet logic (or NML) [5, 6]. In NML devices, binary information is represented by the state (magnetization direction) of single domain nanomagnets and the magnetically represented information is propagated and processed by magnetic dipole–dipole interactions. From the circuit architecture point of view, NML builds on the concept of “quantum-dot cellular automata” [7] – they both share the idea of representing binary signals by bistable nanosystems and processing them through field-interactions. For this reason, nanomagnet logic was formerly called “magnetic quantum-dot cellular automata” (QCA), or field-coupled computing.

Introduction

It is now well recognized that energy dissipation in microchips may ultimately restrict device scaling – the downsizing of physical dimensions that has fueled the fantastic growth of the microchip industry so far [1–6]. But there is a fundamental limit to the dissipation that can be achieved in the transistors that are at the heart of almost all electronic devices. Conventional transistors are thermally activated. A barrier is created that blocks the current and then the barrier height is modulated to control the current flow. This modulation of the barrier changes the number of electrons following the exponential Boltzmann factor, exp(qV / kT). This, in turn, means that a voltage of at least 2.3kT / q (which translates to 60 mV at room temperature) is necessary to change the current by an order of magnitude. In practice, a voltage many times this limit of 60 mV has to be applied to obtain a good ratio of on- and off-currents. As a result, it is not possible to reduce the supply voltage in conventional transistors below a certain point, while still maintaining the healthy on/off ratio that is necessary for robust operation. On the other hand, continuous downscaling is putting an ever larger number of devices in the same area, thereby increasing the energy dissipation density beyond controllable and sustainable limits. This situation is often called Boltzmann’s Tyranny [2], and it has been predicted that unless new principles can be found based on fundamentally new physics, then transistors will die a thermal death [4].

What is a low-power switch?

Transistors in the traditional field effect geometry operate by the injection of mobile carriers – electrons or holes – from a source reservoir to the drain reservoir through a conducting channel region. The carriers enter the channel region by surmounting an electrostatic potential barrier. The gate electrode controls the height of this barrier capacitively. The carriers in the source reservoir are in thermal equilibrium with the source contact. This means that the carriers, say electrons, are distributed in energy in the conduction band according to the Fermi–Dirac distribution f(E = 1/1[1+exp((E − EF)/kT)]. The Maxwell–Boltzmann approximation f(E) ~ exp[− E/kT] of the Fermi–Dirac distribution for large energies represents the high-energy tail of the distribution. There are electrons in this tail with energy higher than the potential barrier; the gate cannot stop them from being injected into the channel. This leads to a sub-threshold “leakage” drain current ID ~ exp[qVGS / kT], which leads to the well-known sub-threshold slope (S) requirement of S ~ (kT / q)ln10 ~ 60 mV/dec change of current. Methods to make the SS steeper than the 300 K value of 60 mV/dec value are expected to substantially lower the power dissipation in digital logic and computation [1, 2]. The methods must explore novel mechanisms of charge transport, or of electrostatic gating. This chapter focuses on transport.

The high-energy tail of electrons exists because of the available density of states (DOS) DC(E) of the conduction band; the electron distribution in energy is n(E) = DC(E)f(E). If the DOS were cut off, there would be no tail, and it is possible to obtain S less than 60 mV/dec. This sort of energy filtering is possible if we replace the n-type source for electrons by a p-type source, which has a valence band maximum and zero DOS above. For injection into the channel of the n-FET, the electrons cannot undergo the traditional drift/diffusion process, but have to quantum mechanically tunnel through the bandgap. This energy-filtering scheme to achieve sub-60 mV/dec switching is the central idea behind the tunneling FET (or TFET).

Introduction

Nanomagnetic or spintronic circuits hold the promise of non-volatile and reconfigurable logic with low switching energy. One such circuit is the magnetic majority gate formed by concatenating several magnetic tunnel junctions together in such a manner that they interact with each other through a common ferromagnetic free layer to achieve the desired functionality. A key advantage of this configuration is that multiple majority gates can be concatenated together entirely in the magnetic domain without conversion to electric signals. The magnetic majority gates can in turn be concatenated together to form more complex circuits, such as a full magnetic adder circuit described here and simulated with a micromagnetic solver. The dynamics of magnetic polarization propagate through the adder circuit via the motion of magnetic domain walls and correspond exactly to the propagation of information through a ripple adder circuit. The switching speed and energy of the fundamental magnetic switching operation in the magnetic adder is comparable to the same fundamental switching operation in single magnetic gates or nanomagnetic memories. It provides a basis for estimating the operational speed and energy of the more complex magnetic circuits. A non-linear transfer characteristic ensures noise margin and signal restoration after every operation critical for Boolean logic.

The most common applications of spintronic devices in production today are non-volatile memories, namely magnetic random access memory (MRAM), which employ field induced switching of magnetic polarization. More recently, however, a much more efficient magnetic switching mechanism, based on current-induced switching, has been introduced and used to fabricate spin transfer torque RAM (STTRAM) memories [1]. It is natural to consider extending the physics of STTRAM to other magnetic logic functions [2], including the spin torque majority gate (STMG) described here. One obvious benefit of magnetic logic circuits is they are non-volatile, and hence do not suffer from standby power dissipation. A related benefit is that they can be turned on instantly since the circuit is non-volatile in the absence of input signals. In spite of these obvious advantages and the fact that numerous spintronic logic devices have been proposed, few of them have been fabricated and none have been demonstrated to function in an integrated circuit.

Overview

Over the past several decades, CMOS (complementary metal–oxide–semiconductor) scaling has come to be associated with dramatic and simultaneous improvements in functionality, performance, and energy efficiency. In particular, although the actual historical trends did not uniformly follow a single type of scaling, there was a relatively long period of “Dennard scaling” [1] during which the quadratic (with scale factor) improvements in transistor density were accompanied by a quadratic reduction in power per gate despite a linear increase in switching frequency. All of this was achieved by scaling the operating (i.e., supply) voltage of the circuitry linearly along with the lithographic dimensions of the transistor. Ideally, this would result in constant power consumption per unit chip area, making it relatively easy for chip architects and designers to exploit the increased transistor density with a fixed chip area (and hence power) to cram more functionality into a single die.

Unfortunately, however, as Dennard himself predicted, because of the fact that some intrinsic parameters associated with transistor operation – in particular, the thermal voltage kT/q – do not scale along with the lithographic dimensions, this type of scaling came to an end in the early 2000s. Up until that point, because leakage currents (and hence leakage energy) were essentially negligible, the transistor’s threshold voltage had been treated as a scaling parameter that could be reduced with no significant consequence. However, since leakage current depends exponentially on the threshold voltage, this type of scaling indeed eventually came to a halt.

Introduction

A spin wave is a collective oscillation of spins in a spin lattice around the direction of magnetization. Similar to lattice waves (phonons) in solid systems, spin waves appear in magnetically ordered structures, and a quantum of a spin wave is called a “magnon.” Magnetic moments in a magnetic lattice are coupled via the exchange and dipole–dipole interaction. Any local change of magnetization (disturbance of magnetic order) results in the collective precession of spins propagating through the lattice as a wave of magnetization – a spin wave. The energy and impulse of the magnons are defined by the frequency and wave vector of the spin wave. Similar to phonons, magnons are bosons obeying Bose–Einstein statistics. Spin waves (magnons) as a physical phenomenon have attracted scientific interest for a long time [1, 2] and a variety of experimental techniques including inelastic neutron scattering, Brillouin scattering, X-ray scattering, and ferromagnetic resonance have been applied to the study of spin waves [3, 4]. Over the past two decades, a great deal of interest has been attracted to spin wave transport in artificial magnetic materials (e.g., composite structures, so-called “magnonic crystals” [5, 6]) and magnetic nanostructures [7–9]. New experimental techniques including time-domain optical and inductive techniques [7] have been developed to study the dynamics of spin wave propagation. In order to comprehend the typical characteristics of the propagating spin wave, we will refer to the results of the time-resolved measurement of propagating spin waves in a 100 nm thick NiFe film presented in [8]. In this experiment, a set of asymmetric coplanar strip (ACPS) transmission lines was fabricated on top of permalloy (Ni81Fe19) film. The strips and magnetic layer are separated by an insulating layer. One of the transmission lines was used to excite a spin wave packet in the ferromagnetic film, and the rest of the lines located 10 μm, 20 μm, 30 μm, 40 μm, and 50 μm away from the excitation line were used for detection of the inductive voltage. When excited by the 100 ps pulse, spin waves produce an oscillating inducting voltage, which reveals the local change of magnetization under the line caused by the spin wave propagation.

Overview

Electron devices with components that undergo phase transitions can add new functionality to classical devices such as field effect transistors and p-n junctions. In this chapter we examine recent research on utilizing phase transition materials, such as but not limited to vanadium dioxide (VO2), for electronics and provide a perspective on how phase transition electronics may complement and add function to complementary metal–oxide–semiconductor devices in emerging computing paradigms. In parallel, there is continuous need to innovate in high-frequency communications, reconfigurable devices and sensors. These fields sometimes may not directly overlap with research directions in computing, however, when new materials are being explored, a variety of interesting properties are uncovered and there is cross-pollination of ideas. In correlated oxides too, studies motivated by fast switching properties have created broad interest such as in the microwave device arena and are considered here for completeness. It is finally pointed out that ionic conduction in oxides or ion-mediated electronic phase transitions induced for example in electric double layer transistors or their solid-state counterparts could play a significant role in future research and development of such correlated electron material systems. Although operationally slower than solid-state devices, liquid gates offer new directions to explore paradigms in reconfigurable fluidic devices that have seen substantial growth in the soft matter fields.

Introduction

Scaling of the metal–oxide–semiconductor field effect transistor (MOSFET) has sustained the growth of the microelectronics industry for numerous decades. As the gate length of these transistors approaches the sub-10 nm regime, it is becoming increasingly difficult to enhance device performance metrics such as energy efficiency and switching speed accordingly. The fundamental limit of complementary metal–oxide–semiconductor (CMOS) scaling that originates from the basic operation principle of MOSFETs has motivated researchers to look for alternative computation component/architecture to complement current CMOS technology. Currently, this is perhaps one of the most important problems in the condensed matter community and has great significance to continued growth of the hard sciences in academia.

Introduction

Tunneling field effect transistors (TFETs) have the potential to achieve a low operating voltage by overcoming the thermally limited sub-threshold swing voltage of 60 mV/dec [1], but results to date have been unsatisfying. The low-voltage operation is parameterized by the voltage required to obtain a 10× change in output current, called the sub-threshold swing voltage, S. The best reported sub-threshold swing voltage has been measured at a low current density of ~1 nA/μm, but unfortunately becomes significantly larger as the current increases. When trying to design a new low-voltage switch to replace the transistor, there are three major requirements to be fulfilled:

• The sub-threshold swing voltage needs to be much steeper than 60 mV/dec and ideally only a few millivolts per decade to reduce the operating voltage.

• A large on/off ratio of around 106/1 is needed to suppress leakage currents.

• A high conductance density around 1 mS/μm (or 1 mA/μm at 1 V) is needed so that the switch can be significantly smaller than the wire that it drives while maintaining a high speed.

While devices have been built that meet one or two of the three requirements, to date no logic switch meets all three requirements [1, 2]. No one has achieved a steep sub-threshold swing voltage at a high conductance.

To understand this, we first consider a simple tunneling diode in Sections 5.2–5.6 to understand the essential physics of tunneling and then in Sections 5.7–5.9 we consider the additional complexities of building a full transistor. In TFETs the challenge is complicated by the existence of two switching mechanisms. The gate voltage can be used to modulate the tunneling barrier thickness and thus the tunneling probability [3–6] as shown Fig. 5.1(a) and (b). The thickness of the tunneling barrier can be controlled by changing the electric field in the tunneling junction. Alternatively, it is also possible use energy filtering or density of states switching as illustrated in Fig. 5.1(c) and (d). If the conduction and valence band do not overlap, no current can flow. Once they do overlap, current can flow.