So what really happens when a program loads? When an interrupt event occurs? Well, a lot!

In addition, packaged logic gates are low density, typically containing only a few gates.1 That means any reasonably complex digital systems might need tens or hundreds of DIP packages. Because signals have to travel between packages, systems built with discrete logic are limited in speed as well.

AoE works a similar problem in detail: §2.2.5A. The example below differs in describing a follower for AC signals. That makes a difference, as you will see, but the problems are otherwise very similar.

In the last chapter’s Worked Examples, we looked at several digital comparators constructed out of gates. We certainly could translate those to structural models in Verilog, but that misses the point. The advantage of an HDL is it frees us from truth tables, Boolean equations, and the need to implement the result with logic gates. Instead, we can describe the desired result behaviorally.

Use a logic probe, not DVM or – worse – your eyes This should go without saying, but we’re not sure it yet does. We find it boring to stare at a wire, trying to see if it goes where it should.

Defines the level (high or low) in which a signal is “True,” or – better – “Asserted” (see next term). We avoid the former because many people associate “True” with “High,” and that is an association we must break.

Here we will do a problem much like the one we did more sketchily in . If you are comfortable with the design process, skip to §§3W.1.6 and 3W.1.7, where we meet some new issues.

In the lab exercises, from now and ever after, you will want to be able to read resistor values without pulling out a meter to measure the part’s value (we do sometimes find desperate students resorting to such desperate means). The process will seem laborious, at first; but soon, as you get used to at least the common resistance values, you will be able to read many color codes at a glance.

Here’s a statement of the design task, and some questions:

We want to solve the problem of optimizing circuit performance by selecting from the great variety of available op-amps. We will try to make sense of the fact – not predictable from our first view of op-amps as essentially ideal – that there are not one or two op-amps available but approximately 30,000 listed (on the day of this writing) on one distributor’s website (DigiKey).

The problem – just analysis this time: This is a rare departure from our practice of asking you to design, not to analyze. Inventing a difference amp1 seemed a tall order, and, on the other hand, the difference amplifier’s behavior seems far from obvious. So, here’s a little workout in seeing how the circuit operates.

Serial data input and output are classic applications where interrupt-driven I/O makes sense. Rather than sit in a loop wasting CPU cycles waiting for each byte to be sent or received, an ISR can load a new byte into the output register each time the previous byte has been sent, or store each new byte in a buffer as they are received.

Please check the errata page at https://LAoE.link/Installing_the_FPGA.html before you begin to see if there have been any updates or changes to the procedure below.

Insert the shorter pins of the 2x5 SWD header from the top of the board and solder from the rear. Use care to avoid solder bridges on the closely spaced pins of this connector: see Fig. 22S.2.

Why? Finite State Machine design methodology provides a rigorous way to design synchronous systems. It applies not only to hardware but to software design as well (as we shall see when we study embedded microcontrollers).

Now that we have seen that sequential circuits are almost always (the SR and transparent latches being the exceptions) designed with edge-triggered logic, we need to look at what can go wrong with edge triggering if we are not careful.