MRS Online Proceedings Library (OPL)

We have grown GaAs directly on silicon substrates by molecular beam epitaxy (MBE) at low substrate temperatures (∼250 °C). The silicon wafer surface cleaning and GaAs film growth processes were done at temperatures lower than the Si-Al eutectic temperature, in order to enable monolithic integration of low-temperature-grown-GaAs (LT-GaAs) photoconductive switches with Si-CMOS circuits. In situ reflection high-energy electron diffraction (RHEED), ex situ x-ray diffraction (XRD) and atomic force microscopy (AFM) studies were performed to characterize the LT-GaAs film quality. The film surfaces show less than 1 nm root-mean-square (rms) roughness and the anti-phase domain (APD) density is below the XRD detection limit. Metal-semiconductor-metal (MSM) photoconductive switches were made using this material. A time-resolved electro-optic sampling technique was used to determine the responsivity and speed of the switches. A full-width at half-maximum (FWHM) switching time of ∼2 picoseconds was achieved and the responsivity of switches made from LT-GaAs on Si material was comparable to that of switches made from LT-GaAs on GaAs material.

Direct integration of sol-gel derived ceramic films with porous silicon, without buffer layers, has been demonstrated. The effects of ceramic type, solvent type, solution concentration, as well as, porous silicon layer thickness, porosity and preparation conditions, on the quality and microstructure of sol-gel films/porous silicon integrated systems have been studied. The following ceramic compositions have been applied to porous silicon as protective coatings: PZT (PbZr0.3Ti0.7O3), PLZT (Pb0.925La0.055Zr0.3Ti0.7O3), ZrO2, TiO2, with 2-methoxyethanol and 2-ethoxyethanol solvents, 0.5 and 0.1 M precursor solution concentrations. The LSCO (La0.5Sr0.5CO.3) water based sol-gels have been deposited for electroconductive purposes.

The best compositions for integration, giving transparent, mirror-like, uniform ceramic films with fine morphology and strong adhesion, were found to be the TiO2 and ZrO2 as well as, the diluted (0.1 M) PZT (PbZr0.3Ti0.7O3) sol-gel precursors. Conductive LSCO sol-gel derived films showed improved wetting and stronger adhesive interaction with porous silicon, as compared to polished silicon wafers.

Ru and RuO2 thin films were deposited on (100)LaAlO3 (LAO), (100)MgO and (111)Pt/Ir/ SiO2/Si substrates byMOCVD. Pb(Zr,Ti)O3 (PZT) was fabricated on Ru/LAOand RuO2/LAO. Ru thin films deposited at 400°C or higher on LaAlO3 and MgO showed epitaxial (001) crystal orientation. (001) uniaxial Ru was deposited on Pt/Ir/SiO2/Si. RuO2 thin films with (100) orientation were deposited both on LaAlO3 and Pt/Ir/SiO2/Si. (110)-oriented RuO2 thin film was deposited on MgO. Epitaxial RuO2 thin films were deposited on LaAlO3 and MgO at 400°C or higher. The smoothest surfaces and the lowest room-temperature electrical resistivities were obtained at 400°C and 450°C, respectively. The crystal orientations and electrical properties of the PZT thin films deposited on the Ru and RuO2 thin films at 550°C were strongly affected by the crystal orientations and microstructure of the Ru and the RuO2 films. Rhombohedral Pb(Zr0.6Ti0.4)03 thin films deposited on RuO2/LAOand Ru/LAO at 550°C with lower growth rate (1.2nm/min) showed (110) and (001) orientation, respectively. The remanent polarization value (Pr) for (001) PZT on Ru/LAO was ∼70 μC/cm2. (110) PZT on RuO2/LAO showed lower Pr (∼30 μC/cm2), but showed low leakage current (10-9 A/cm2 at 500kV/cm). The dense microstructures and smooth surface structures brought the good leakage characteristics.

For the fabrication of bulk strained Si devices, a thin Si layer is deposited on a virtual substrate consisting of a several μm thick compositionally graded SiGe layer. A simpler approach utilizing H or He implantation to enhance relaxation of a thin SiGe film was recently reported. In this current work, hydrogen implantation is used to enhance the SiGe relaxation; and, relaxation beyond the previous reported limit is demonstrated. Experiments are performed on CVD deposited SiGe films with Ge fractions ranging from 20% to 40 % and thickness in the range of 100nm to about 500nm. After annealing at 800°C, relaxation of more than 80% is achieved. PMOS and NMOS devices are successfully fabricated and much enhanced hole and electron mobilities are demonstrated.

The surface topography of Si(100) modified by low energy Ar+ bombardment was characterized by Atomic Force Microscopy (AFM). AFM images show that ripples can be formed by 500eV Ar+ at incidence angle 40°. The spacing wavelength of ripples is around 70nm with wave vector parallel to the projected direction of ion beam. Direct bonding and mechanical delamination of Si wafer pairs with ripples are investigated. Delamination energy measured by crack-opening method along the direction perpendicular to the wave vector,γ⊥, is always smaller than that along the wave vector direction,γ„; Both γ⊥ and γ„ are found to decrease with sputtering time. The AFM images after delamination indicate that the bonding and delamination process do not eliminate the ripples on the wafer surface.

Presented theoretical paper concerns the structure investigation of Si/SiGe/Si heterojunction bipolar device by the extremely sensitive Grazing-angle Incidence X-ray Backdiffraction (GIXB) technique. The silicon cap layer and the silicon substrate have the same value of the spacing period along the growth surface according the proposed model of heterostructure. However, a longitudinal space shift exists between their lattice space periods. Appearance of the space shift is stipulated by the interface misfit dislocations. The magnitude of the space shift is one of the important characteristics of crystalline layers and substrate interface quality, and can be used for the non-destructive control of device parameters during the growth and fabrication processes.

We show that SiGe grown on free-standing silicon is elastically relaxed. The free-standing Si structure consists of a ∼30 nm-thick, 5 μm-square silicon slab supported by a SiO2 pedestal at a single contact point at the center of the square (the cross-section resembles a mushroom). A matrix of free-standing structures was made by patterning a bonded silicon-on-insulator (SOI) wafer and undercutting the SiO2 to form the pedestal. Un-patterned areas of the SOI wafer and the exposed bulk Si substrate were included as reference regions. A UHVCVD Si0.8Ge0.2 film, about 200 nm-thick, was grown epitaxially on both sides of the free-standing silicon and the surrounding exposed bulk Si. The SiGe was also grown on the un-patterned SOI and bulk substrate control areas. The SiGe film grown on both SOI and bulk silicon was found to be fully strained. In contrast, the SiGe layer grown on free-standing silicon is ∼89% strain-relaxed, and the free-standing silicon film was measured to be under tensile strain. Since the same lattice mismatch was found between the SiGe layer and the Si on the free-standing silicon and on the SOI and bulk Si control regions, we conclude that the strain relaxation of the SiGe film on freestanding Si is elastic with the strain accommodated entirely by the free-standing silicon film under tensile strain. This was further confirmed by AFM measurements. The SiGe film on the control regions showed a very smooth SiGe surface with only a few surface steps originating from misfit dislocations at the SiGe/Si interface. No surface steps from misfit dislocations were observed on the surface of the SiGe film on free-standing Si. These results show that freestanding silicon serves as an ideal compliant substrate for SiGe.

Relaxed, high Ge content SiGe layers have been realized using stress balance on acompliant borophosphorosilicate glass (BPSG). A 30-nm fully-strained Si0.7Ge0.3 layer wastransferred onto a 1 μm BPSG film by wafer-bonding and Smart-cutρ processes, after which thecontinuous Si0.7Ge0.3 film was patterned into small islands to allow for lateral expansion. Afterthe strain in Si0.7Ge0.3 islands was released by the lateral expansion resulting from the flow of theBPSG, a Si0.4Ge0.6 layer was commensurately deposited under compression. Upon equilibriumafter an annealing, stress balance was formed between the SiGe films, resulting in a larger inplanelattice constant than that of relaxed Si0.7Ge0.3. With a thiner (6 nm) Si0.7Ge0.3 starting film,an in-plane lattice constant equivalent to fully-relaxed Si0.45Ge0.55 has been obtained.

High dielectric constant (k), the thermal stability and the chemical stability with respect to reaction with silicon of hafnium oxide (HfO2), and zirconium oxide (ZrO2) places them among the leading candidates for an alternative gate dielectric material. High dielectric constant HfO2 and ZrO2 thin films have successfully been deposited on silicon substrates at a temperature of 27 °C by Laser Assisted Molecular Beam Deposition (LAMBD). The LAMBD process is related to conventional Pulsed Laser Deposition (PLD). In the PLD process, the ablation plume impinges directly upon the substrate to deposit the thin film, whereas in the LAMBD process, the ablation material is expanded within a concurrently pulsed stream of a reactive gas. The gas pulse serves both to create the desired material and to transport the material to the substrate for deposition of the thin film. One advantage of the LAMBD process is that a chemically reactive carrier gas can be selected to produce the desired chemical products. Depositions yielded 35 nm to 135 nm thick HfO2, and ZrO2 films.

Structural and chemical characterization of the films were performed by Auger electron spectroscopy (AES), Rutherford back-scattering (RBS), scanning electron microscopy (SEM), and x-ray diffraction (XRD). Film surface was investigated by atomic force microscopy (AFM) while optical characterization was also performed by means of spectroscopic ellipsometry (SE). Within the process window investigated, the film Hf/O and Zr/O ratios was found to be in the range 0.6 to 1.2. The as deposited films were amorphous with refraction index (RI) at 623 nm wavelength films in the range of 1.22 to 1.27 for the HfO2 and in the range of 1.23 to 1.19 for the ZrO2 films.

Effects of grain orientation on the electrical polarization and leakage current characteristics of Bi3.25La0.75Ti3O12 (BLT) thin films have been investigated with respect to c-axis off-alignment. The BLT thin films from epitaxially aligned along c-axis to (117) and (014) off-aligned orientations have been successfully grown by using both different electrode materials (Pt and SrRuO3) and heat-treatments. In order to evaluate the crystallinity and the film texture of various off-aligned BLT thin films, X-ray diffraction (XRD) and transmission electron microscopy (TEM) were carried out. The BLT thin films deposited on SrRuO3/SrTiO3 (100) substrate was grown epitaxial c-axis alignment. That is, the c-axis of the film was completely parallel to the substrate normal, resulting in a cube on cube epitaxial relationship with the underlying SrRuO3 film. The corresponding P-E curve showed nearly paraelectric property. The polycrystalline (117) and (014) oriented BLT thin films revealed that remnant polarization increased remarkably due to the anisotropy of spontaneous polarization of BLT. The surface roughness of BLT thin films was increased to result in degraded leakage current characteristic. According to the present results, it can be concluded that the grain orientation of BLT thin films is a crucial factor controlling the polarization properties and leakage current characteristics.

Layer separation of He+-ion implanted relaxor ferroelectric films (0.955)[Pb(Zn1/3Nb2/3)O3]–(0.045)[PbTiO3] (0.955PZN-0.045PT) has recently been reported in the literature.[1,2] Here we report on optical and X-ray diffraction analysis of the implanted material prior to separation. The formation of optical waveguides as a result of He+-ion implantation enables us to probe the sacrificial layer. A large refractive index contrast is observed between this layer and the film. Significant tetragonal distortions are also seen in the waveguide region (“the film”). Rapid thermal processing (RTP) significantly changes the peak position of the index contrast profile, possibly indicating a large redistribution of stress by He evolution in the sacrificial layer. A commensurate reduction in tetragonal distortion and local strain distribution in the waveguide region to values close to those observed before implantation is measured by triple crystal high resolution X-ray diffraction.

A study of the interfacial properties of wafer bonded InP/Si is presented. The electrical properties are measured by bonding InP to Si with different doping concentrations and by measuring the current voltage characteristics of the bonded pairs. Two different kinds of structures are studied: 1) n+InP doped to 3×1018 cm-3 bonded with n+Si doped to 1×1019 cm-3, and 2) n+InP doped to 3×1018 cm-3 bonded with p-Si doped to 6×1014 cm-3. After a 350°C anneal, structure 1 shows low resistive ohmic behavior while structure 2 is rectifying due to its higher sensitivity to interfacial chemistry. Indeed, both the reverse and forward current are reduced by annealing in structure 2, suggesting the formation of an interfacial barrier during annealing. This hypothesis is supported by High Resolution Transmission Electron Microscopy combined with Fourier Transform Infrared Spectroscopy, which indicate the formation of an amorphous interfacial oxide from the reaction of adsorbed water trapped at the InP/Si interface.

We report on a study of vacuum-deposited thin films of C60 fullerene on Si (100) and InP (100) semiconductor surfaces. The film morphology and C60—substrate interactions were investigated by using atomic force microscopy (AFM) and Fourier transform infrared spectroscopy (FTIR). For the film deposition, both patterned Si aand InP surfaces were used. It was found that the stronger interactions occur between C60 molecules and Si surface, than between C60 molecules and InP surface. On InP surface with microrelief of parallel V-grooves oriented in [011] direction, C60 films grow preferentially above the groove walls, with C60 grains arrayed in the direction perpendicular to the groove axis.

A novel ultra-low-thermal-budget pixel-to-point transfer process based on the excimer laser lift-off and Pd-In transient-liquid-phase bonding scheme was developed for flexible and precise placement of single pixels of GaN-based light-emitting diodes (LED) on target substrates. The transfer was accomplished by (1) temporarily bonding the light-emitting diode (LED) pixel to a specially designed pick-up rod with sapphire substrates facing up using Super Glue., (2) removing the sapphire substrates using laser lift-off, and (3) registering and permanently bonding the LED pixel to the designated area in the target substrates using Pd-In transient-liquid-phase bonding. An oxygen plasma was employed to remove the Super Glue® residue before further microfabrication and system integration was performed. The capability of this technique was demonstrated in the integration of GaN-based LED pixels with pre-fabricated PIN photodiode chips and thin-film bandedge filters, which formed the non-disposable subsystems of a fluorescence-based lab-on-a-chip system. The performance of these integrated LED pixels and the integrated microsystems has been assessed by evaluating the fluorescence intensity as a function of equivalent fluorescein dye concentration using disposable polydimenthyl siloxane(PDMS) microfluidic channels. GaN LEDs with peak emission at 463 nm were used to excite 515nm fluorescence from FluoSpheres® carboxylate-modified fluorescent microspheres (40nm in diamters).

Bonding of polished, polycrystalline diamond films to silicon was performed in ultra high vacuum at 32 MPa of applied uniaxial stress. The transmission electron microscopy (TEM) investigation revealed that the interface of all bonded samples was non-uniform. An abrupt boundary between the two wafers existed only in some parts of the interface, while other parts contained an amorphous interlayer of up to 40 nm in thickness. Electron energy loss spectroscopy (EELS) revealed that this interlayer consisted of oxygen, carbon and silicon. Based on comparison of the microstructure and chemical composition of the interface formed at different bonding temperatures, we propose a model for the silicon/diamond wafer fusion process.

Atomic wafer fusion of GaSb to GaAs, and the transfer of epitaxial GaSb/GaInAsSb/GaSb heterostructures to GaAs by fusion and substrate removal are demonstrated for the first time. Wafers and epilayers were fused with or without application of mechanical pressure at temperatures as low as 350 °C. A periodic pattern of grooves etched into the GaAs wafer and an overpressure of As and Sb vapor were used to improve covalent bonding. Varying degrees of mass transport and covalent bond formation between wafers were observed in cleaved crosssections under high-resolution scanning electron microscopy. Epilayers fused without pressure application exhibited significantly better structural and optical properties compared to those fused with pressure.

The use of alternative channel materials such as germanium [1,2] and strained silicon (ε-Si) [3-5] is increasingly being considered as a method for improving the performance of MOSFETs. While ε-Si grown on relaxed Si1-xGex is drawing closer to widespread commercialization, it is currently believed that almost all of the performance benefit in CMOS implementations will derive from the enhanced mobility of the n-MOSFET [5]. In this paper, we demonstrate that ε-Si p-MOSFETs can be engineered to exhibit mobility enhancements that increase or remain constant as a function of inversion density. We have also designed and fabricated ε-Si / ε-Ge dual-channel p-MOSFETs exhibiting mobility enhancements of 10 times. These p-MOSFETs can be integrated on the same wafers as ε-Si n-MOSFETs, making symmetric-mobility CMOS possible.

The unique properties of superconductors such as radiation hardness and high microwave performances [1-3] make the integration with semiconductor conventional electronics a stimulating challenge. Many attempts have been tried to obtain good quality YBa2Cu3O7-x (YBCO) films on Si substrates, with the aim of taking advantage from the properties of both materials, but interdiffusion reactions and a poor lattice and thermal expansion coefficient matching require the use of a buffer layer at the semiconductor/superconductor interface. Yttria-stabilized zirconia (YSZ), Y2O3, MgO, SrTiO3, CeO2 and their combinations have been proposed and used as buffer layers in the case of Si/YBCO systems. In this paper we report on annealing treatments performed on Si/CeO2 bilayers. A set of optimized samples with deposition temperatures ranging from 100°C to 800°C has been radiatively heated at two different annealing temperatures, in N2 and O2 atmospheres. All the samples have been characterized by X-ray diffraction, Atomic Force Microscopy, micro-Raman spectroscopy. The preferential grain orientation, the lattice parameter, the crystals dimensions, the surface roughness have been studied. As a preliminary tentative, we report on YBCO film growth on the top of CeO2/Si optimized bi-layer before undergoing annealing treatment. This YBCO film resulted to be a-axis preferential oriented, with some contribution of c-axis oriented grains.

All of the materials necessary for integrated isolators were grown and the application of 2D photonic crystal structures to isolators has been explored. Magnetooptical garnets were grown monolithically by reactive rf sputtering. MgO was used as a substrate because it will useful for future buffer layers and optical claddings. The chemical, structural, and optical properties of the resulting films were analyzed. In order to incorporate photonic crystal structures into the magneto-optic integration scheme, we have calculated a range of radii and spacings necessary to fabricate YIG/air structures with 2D photonic bandgaps using an advanced plane-wave expansion technique. Selfassembled alumina nanostructures have been grown with similar symmetries as those calculated, namely hexagonal close-packed pores. These nanostructures were grown onto semiconductor and oxide substrates in order to demonstrate their use as RIE masks in fabricating photonic crystals. The nanostructures can also be transferred into YIG using separate alumina masks. However, the actual structures grown in this work were smaller than those required for telecommunications due to power supply limitations. For biasing the magneto-optical elements, sputtering was used to monolithically integrate permanent SmCo magnet films using semiconductor-friendly processing. These magnets were sufficient for biasing our magneto-optical waveguides. The chemical, structural and magnetic properties of these materials, as well as total integration with SiO2 cladding layers were analyzed.

Most studies of Ba0.5Sr0.5TiO3 (BST) thin film deposition have focused on chemical vapor deposition or spin-on techniques. Both these techniques require high substrate temperature (greater than 600 °C), either during the deposition or during an anneal after deposition. A few groups have reported on sputtered films, but most of these studies also used high-temperature processes. While such temperatures are compatible with poly-Si plug DRAM and related technologies, they are far above the limits for technologies that require the deposition of non-refractory metals before the deposition of the ceramic film. For example, the use of Al metalization before the deposition of BST would limit the BST processing temperature to about 450 °C. A process compatible with such a temperature limit is reported. Such a process makes fabrication of high quality BST thin films difficult, primarily due to the need for oxidation and grain growth in the ceramic. The leakage current and dielectric properties of BST films deposited in such a process are reported and are shown to be sufficient for practical device applications.