Beam squinting

Although the delay elements have to compensate a time delay, in practice, phase shifters are commonly used to approximate this behavior. For systems with moderate bandwidths and array sizes, this proves to be a good trade-off, due to easier realization, calibration, and especially exploitation of phase ambiguity.

However, when applied to large arrays or wideband systems, phase shifters cause significant frequency dependency of the scan angle θ ₀, called beam squinting. This is due to the constant phase shift, not corresponding with the correct time delay at all frequencies of operation. Deviation of scan angle $\Delta\theta_0$ at frequency f from $\theta_\text{0,c}$ at center frequency f _c can be calculated using (1) and the phase shifters time delay at frequency f as shown in Equation (3)

(3)\begin{align} \Delta\theta_0 (f) = \arcsin \left( \frac{f_\text{c}}{f} \sin(\theta_\text{0,c}) \right) - \theta_\text{0,c}. \end{align}

As an example, an ideal 1 mm-spaced eight-element linear D-band antenna array at a scan angle $\theta_0 = {45}{^\circ}$ is observed. If phase shifters are used, (3) yields a beam squint of ${-9.39}{^\circ}$ at 170 GHz and ${19.15}{^\circ}$ at 110 GHz, which matches the simulated gain patterns shown in Fig. 2(a). An amplitude error of 5.1 dB, mainly dependent on the main lobe width and therefore the array size, is observed. The timed array’s pattern shown in Fig. 2(b) is not affected by beam squinting and the related losses. It only shows a decreasing main lobe width at higher frequencies, which is due to the larger spacing of antenna elements d relative to the wavelength.

Figure 2.

Array factor of an eight-element, 1 mm-spaced linear array, scanned to $\theta_0={45}{^\circ}$ at $f_\text{c}={140}\,{GHz}$, controlled by (a) ideal phase shift and (b) ideal TTD.

Instantaneous array bandwidth

For communication systems, the demonstrated amplitude loss due to beam squinting is of main interest as it directly affects the channel response. The normalized array factor and therefore also the frequency response of a phase controlled linear array is given by (4) [Reference Balanis2]. Figure 3(a) shows the example case’s array factor frequency response at $\theta_0 = {45}{^\circ}$ that exhibits a loss of 5.1 dB at the band edges which matches the previous observations of Fig. 2(a). The phase response does not contain any phase or group delay distortions as it does not deviate from an ideal time delay which is 0 , if phases are referred to the center element

(4)\begin{equation}AF_\text{n}=\frac1N\left(\frac{\sin\left(\frac N2\psi\right)}{\sin\left(\frac12\psi\right)}\right),\ \psi=\frac{2\pi f}cd\,cos\theta+2\pi f_\text{c}\tau_0.\end{equation}

Figure 3.

Array factor of an eight-element, 1 mm-spaced linear phased / timed array over frequency, steered to $\theta_\text{0,c} = {45}{^\circ}$ and received at (a) ${45}{^\circ}$ and (b) ${50}{^\circ}$.

A phased array’s 3 dB bandwidth can be directly calculated from (5), resulting in 46.99 GHz for the uniformly illuminated case (beam broadening factor $B_\text{b} \approx 1$) [Reference Mailloux3]

(5)\begin{align} BW_\text{ps,arr,3dB} = \frac{0.886 B_\text{b} c}{N d \sin(\theta_\text{0})}. \end{align}

Considering the applicability of phased arrays to millimeter-wave transmitter systems, a misalignment between beam direction and actual placement of the receiver must be taken into account. Figure 3(b) shows the normalized array factor over frequency if the receiver is located at an angle of ${50}{^\circ}$ while the phase shifters are still configured for ${45}{^\circ}$. As some of the beams in Fig. 2(a) have a steep slope at ${45}{^\circ}$, a drastic increase in loss is observed, while only little additional loss is caused by the timed array.

Intersymbol interference in phased arrays

In phased arrays, only carrier phases are aligned using a constant phase shift which has no influence on the group delay and therefore the signal envelope remains unaffected. Thus, phased array imperfections under perfect beam alignment can be also described by the envelope delay difference τ ₀ between elements. This effect causes intersymbol interference (ISI), similar to multipath propagation, with a maximum path length difference of $(N-1)\tau_0$, degrading error vector magnitude of digitally modulated signals.

A mitigation technique, including a case study for 5G signals, using digital equalization is thoroughly described in [Reference Zhang, Yin and Rebeiz4]. In the course of this work a simulation model closely following [Reference Zhang, Yin and Rebeiz4] has been created as shown in Fig. 4(a) which is applied to the previous example case. The model passes a 60 GSa/s sampled impulse through a root-raised-cosine filter, N different delays, representing the phased array, and another root-raised-cosine filter to be finally processed by a $N+1$ tap linear equalizer.

Figure 4.

(a) Baseband phased array model with equalizer, (b) intersymbol interference of shaped and delayed impulses, (c) impulse response of undistorted, distorted, and equalized signals in digital baseband, and (d) amplitude (solid) and phase response (dashed) of $\frac{x_\text{tx}}{x_\text{rx}}$ and the equalizer taps.

As expected, Fig. 4(c) shows that the distortion introduced by the array is compensated by the equalizer. Transformation into frequency domain, depicted in Fig. 4(d), further shows that the array factor loss described by this model coincidences well with the calculations of the previous section. From the frequency response, it is also apparent that the equalizer compensates the losses of the phased array and additionally introduces a constant delay of four symbol periods. However, as the equalizer operates in digital baseband it requires sufficient power amplifier back-off respectively signal-to-noise ratio to compensate the loss of array gain, which makes it suitable if moderate loss is introduced by beam squinting. If link budget is more severely degraded, the use of timed arrays instead of phased arrays might be a better option to completely avoid beam squinting.

Array architectures

Phase ambiguity greatly simplifies the realization of phased arrays over timed arrays as covering a certain delay range is not an issue and amplitude calibration can be directly implemented by vector phase shifters. In contrast, TTD elements often have limited delay range, finite resolution, bigger size and are generally more expensive, which lead to the development of several approaches for combining TTD elements with phase shifters.

One approach is to use a dedicated control path for every antenna element, e.g. phase shifter, TTD element, or a cascade of both. References [Reference Mailloux3, Reference Mailloux5] give a detailed description of array pattern errors due to periodic control errors, e.g. introduced by quantized phase shift or TTD that causes a triangular delay error over M _Q antenna elements until $M_\text{Q} \tau_0$ is a multiple of the delay element's least significant bit (LSB). The introduced error can be modeled as subarrays with M _Q elements whose scan angles deviate from the intended scan angle θ ₀. Thus, the zeros of the M _Q-element subarray patterns do not align with the lobes of the array of subarrays which is why quantization lobes appear in the array pattern. The first order quantization lobes occur at an angle of $\theta_\text{Q} = \arcsin \left( \sin(\theta_0) \pm \sin(\frac{c}{f M_\text{Q} d}) \right)$ and have a level according to (6). The worst case level is reached for $M_\text{Q} = 2$ which is the case if the delay between contiguous antenna elements is $\tau_0 = 1.5 \tau_\mathrm{LSB}$ [Reference Mailloux3]

(6)\begin{equation}QL_\mathrm{dB}/(\mathrm{dB}) \lesssim 4 - 6.02N,\ N=-log_2(f \tau_\mathrm{LSB}) \geq 3.\end{equation}

A second approach is to partition larger timed arrays into smaller, sufficiently wideband, phase controlled, contiguous subarrays that are time controlled at their subarray ports. This approach increases the bandwidth according to (5) by a factor equal to the number of M-element subarrays Q, compared to a purely phase controlled array, effectively replacing N by M in (5). As beam squinting causes the M-element phased subarrays’ scan angle to deviate from the intended angle, sidelobes appear. As the number of elements M is given by geometry, the lobes’ angles can be calculated analogously, whereas the pth lobe level is computed by (7) [Reference Mailloux3]

(7)\begin{align} P_{L} = \frac{\pi^2 \left( \frac{d}{c} \Delta f \sin\theta_0 \right)^2}{\sin^2 \pi \left( \frac{d}{c} \Delta f \sin\theta_0 + \frac{p}{M} \right)}. \end{align}

Additionally, quantized TTD at the subarray ports generates another level of subarray grouping with a periodicity of $M_\text{sQ} M$ antenna elements. Quantization lobe levels can be calculated with the same formula by treating the M-element phase controlled subarrays as antenna elements, which reduces the quantization lobe level due to multiplication with the subarray pattern [Reference Mailloux3, Reference Mailloux5]. As the periodicity $M_\text{sQ} M d$ is spatially larger than $M d$, these quantization lobes are closer to θ ₀ than the beam squint lobes. However, if quantization errors are known and reduced quantization lobes can be tolerated at off-center frequencies, one may consider to use the subarrays’ phase shifters to increase the TTD resolution without additional hardware effort.

For mitigation of these grouping effects like the mentioned peak sidelobes or the beam pointing error, several techniques such as randomization, rounding off, or overlapping subarrays are described in literature [Reference Mailloux3, Reference Yajima and Hasegawa6].

Delay integration in frequency converter

Unlike phase shifters that can be reasonably used in the local oscillator (LO) path, TTD has to be integrated into the signal path to benefit from its frequency dependent phase response. Considering the two mixing products of an up-conversion mixer, described by basic addition theorems as shown by (8), alternative concepts to radio frequency (RF) path time delays can be derived. Both mixing products can be phase shifted in the LO and intermediate frequency (IF) path as well as time delayed in the IF path

(8)\begin{align} s_\text{RF}(t) &= \cos \left( \omega_\text{LO} t + \varphi_\text{LO} + \omega_\text{IF} t + \omega_\text{IF} \tau_\text{IF} + \varphi_\text{IF} \right) \nonumber \\ & \quad + \cos \left( \omega_\text{LO} t + \varphi_\text{LO} - \omega_\text{IF} t - \omega_\text{IF} \tau_\text{IF} - \varphi_\text{IF} \right) \end{align}

(9)\begin{align} \varphi_\text{RF,USB} &= {(\omega_\text{LO} + \omega_\text{IF})} \tau_\text{RF} \stackrel{!}{=} \varphi_\text{LO} + \omega_\text{IF} \tau_\text{IF} + \varphi_\text{IF} \end{align}

(10)\begin{align} \varphi_\text{RF,LSB} &= {(\omega_\text{LO} - \omega_\text{IF})} \tau_\text{RF} \stackrel{!}{=} \varphi_\text{LO} - \omega_\text{IF} \tau_\text{IF} - \varphi_\text{IF}. \end{align}

Figure 5.

Timed array system concepts using (a) RF TTD, (b) IF TTD and LO phase shifter, (c) IF phase shifter and TTD for SSB systems, and (d) combined concepts for hierarchical delay concepts.

Several possible approaches are listed in Table 1 and shown in Fig. 5. A linear phase over frequency can be achieved by shifting LO and delaying IF, which is equivalent to an RF path time delay and can therefore be used for all modulation types including in-phase quadrature (IQ) and double sideband (DSB) modulation. In this context, a group time delay (GTD), e.g. [Reference Park and Min7], in the RF path has the same effect as the IF TTD. Assigning the delay functionality completely to the IF path works only for single sideband (SSB) systems, as the second mixing product will be shifted by the inverse IF phase, which is only acceptable if it is discarded. As depicted in Fig. 5(d), functionality can be also combined to achieve subarray and element level controls. It is noted that this combination does not introduce the grating lobes discussed in the previous subsection since TTD is used for element level control.

Table 1.

Equivalent RF delay type of frequency converter integrated delay elements

TTD specifications

TTD elements have to have a bandwidth which is superior to the beam squint induced bandwidth $BW_\text{ps,arr,3dB}$ given by (5) while providing sufficient delay range $\tau_{0,N}$ to cover N antennas as given by (2), in order to reduce the bandwidth limitations of phased arrays. As both parameters depend on the array size, the phased array’s bandwidth can be approximated by (11), only using $\tau_{0,N}$ and the beam broadening factor B _b as variables. Accordingly, Fig. 6 compares the absolute bandwidth of TTD realizations with the calculated phased array bandwidth. At this point, it is noted that the comparison is not perfectly fair as the publications use different definitions of bandwidth, e.g. measurement graphs in [Reference Abbasi and Lee8] indicate less than 3 dB gain variation over the characterized D-band while [Reference Ma, Leenaerts and Mahmoudi9–Reference Hu and Mouthaan12] exhibit a significant negative gain slope

(11)\begin{align} BW_\text{ps,arr,3dB} \stackrel{N\approx (N-1)}{\approx} \frac{0.886 B_\text{b}}{\tau_{0,N}}. \end{align}

Figure 6.

Bandwidth of TTD realizations [Reference Koch, Probst, Breun and Weigel1, Reference Abbasi and Lee8–Reference Govind, Tapen and Apsel23] versus their delay range compared with the phased array bandwidth approximated by (11). Maximum array size and half-power beamwidth (HPBW) related to $\Delta\tau$ according to (2) and (13) [Reference Mailloux3] are shown as additional axes for $\theta_\text{0,max}={45}{^\circ}$ at ${140}\,{GHz}$.

From Fig. 6, it is apparent that many TTD realizations with small delay ranges possess a smaller 3 dB bandwidth than conventional phased arrays. When considering hybrid architectures using phase controlled subarrays, due to sufficient bandwidth, beam squint induced sidelobes must be also taken into account. For example, according to (5), four-element, 1 mm-spaced phased subarrays at 140 GHz and $\theta_0={45}{^\circ}$ still have a bandwidth of almost 94 GHz, but beam squinting causes lobes up to −15.0 dB for a bandwidth of ${\pm}15$ GHz and −7.6 dB for ${\pm}30$ GHz according to (7). Acceptable sidelobe levels depend on the targeted application, but high sidelobes may be problematic for radar applications and communication systems featuring JCAS functionality. A considerably higher bandwidth-delay-product is achieved by moderate frequency, high bandwidth designs up to 50 GHz [Reference Ma, Leenaerts and Mahmoudi9] and 21 GHz [Reference Willms, Ouacha, de Boer and van Vliet10–Reference Hu and Mouthaan12, Reference Cho, Song and Cressler19] that can also be used for sub-THz systems when employed in the IF domain as discussed in Section “Timed and phased arrays”.

TTD elements are expected to avoid beam squinting over a certain bandwidth by providing a constant phase delay τ and therefore a linear phase $\varphi = -\omega\tau$. Correct group delay is not a sufficient criterium for the beamforming functionality as it defines only the slope of the phase. The remaining beam squint due to a deviation of phase and group delay of all-pass delay cells is examined in [Reference Garakoui, Klumperink, Nauta and van Vliet24]. Normally, the relative delay compared to a reference state is of interest as it also describes the tuning range at the antenna port. Referring the forward transmission coefficient $S_\mathrm{21}$ of delay setting B to that of a reference state also removes most of the phase ambiguity and allows easy extraction of relative phase delay and gain variation

(12)\begin{align} S_\text{21,n}(f, B) = \frac{S_\text{21}(f, B)}{S_\text{21}(f, B_\text{ref})}. \end{align}

The resolution of TTD should be high enough for scanning the beam in steps that are smaller than the beamwidth. The smallest step of θ ₀ in fractions of the half-power beamwidth (HPBW) is given by (14) which is derived from (2) and the left of (13) [Reference Mailloux3] as a function of the LSB of the delay $\tau_{0,N}$. For a certain $\tau_\text{LSB}$, smaller steps of the scan angle θ ₀ and reduced HPBW of large arrays cancel each other, giving a constant result. This expression is optimistic as the HPBW can be reduced by element patterns and $\Delta\theta_0$ increases with θ ₀. Further, quantization of intermediate elements is ignored that causes the formation of subarrays

(13)\begin{align} HPBW = \frac{0.886 B_b \lambda}{N d} \stackrel{N\approx (N-1)}{\approx} \frac{0.886 \sin \theta_\mathrm{0,max}}{f \tau_{0,N}} \end{align}

(14)\begin{align} \frac{\Delta\theta_0}{HPBW} \stackrel{N\approx (N-1),\, \sin\theta_0\approx\theta_0}{\approx} \frac{\tau_\text{LSB} f}{0.886 B_\text{b}}. \end{align}

Therefore, another criterion is the level of quantization sidelobes. The worst-case level is approximately given by (6) and applies to element level control as well as timed control at the subarray ports of subarrays. Figure 7 compares both criteria with TTD realizations that have non-continuous control of delay. Realizations at D-band frequencies provide enough resolution for approximately 20 dB of quantization lobe rejection. In the case of a quantized IF path TTD element and high resolution phase shifter, the resulting delay is $\tau_\text{RF} = \frac{\omega_\text{LO}\tau_\text{LO}}{\omega_\text{RF}} \pm \frac{\omega_\text{IF}\tau_\text{IF}}{\omega_\text{RF}}$ and therefore the LSB at the RF port can be calculated to $\tau_\text{LSB,RF} = \frac{\omega_\text{IF}}{\omega_\text{RF}} \tau_\text{LSB,IF}$. Consequently, the resolution requirements of IF path TTD is determined by the IF frequency and not the RF frequency. This means that the resolution in phase matters, not in time. In Fig. 7, it can be seen that many lower frequency implementations also achieve 20 dB quantization lobe suppression, while some of the not shown designs implement continuous high resolution stages [Reference Ma, Leenaerts and Mahmoudi9, Reference Hu and Mouthaan12–Reference Ma, Leenaerts and Mahmoudi14, Reference Govind, Tapen and Apsel23, Reference Lee and Valdes-Garcia26, Reference Shen, Zhang, Yang, He, Guo and Gao27].

Figure 7.

Least significant bit (LSB) of delay $\Delta\tau$ of TTD realizations [Reference Abbasi and Lee8, Reference Willms, Ouacha, de Boer and van Vliet10, Reference Hu and Mouthaan11, Reference Woods, Valdes-Garcia, Ding and Rascoe15–Reference Shin, Yom and Kim17, Reference Cho, Song and Cressler19, Reference Karakuzulu, Eissa, Kissinger and Malignaggi20, Reference Maurette-Blasini, Kuliabin, Chartier and Quay22, Reference Zolkov, Weiss, Madjar and Cohen25] versus their maximum operational frequency compared with the criteria of sub-HPBW resolution, according to (14), and quantization lobe QL suppression according to (6).

Errors of phase and amplitude at the antenna ports generally cause directivity degradation, pointing error and grating lobes. If errors are periodic, strong sidelobes are expected, whereas random errors cause an increase of the average sidelobe level [Reference Mailloux3]. However, a linear amplitude taper due to an expected correlation of loss and delay showed little effect on the peaks of the sidelobes of a rectangular taper, but hinders complete extinction of the array factor’s exponential terms with ${180}{^\circ}$ phase difference.

In contrast to phase shifters which exploit the ambiguity of a periodic signal for large phase differences, TTD elements have to incorporate spacious delay elements. Therefore, a critical parameter is the required chip area for a certain delay. Figure 8 charts the delay range per chip area over the maximum operational frequency. Implementations at lower frequencies tend to achieve a higher delay range per area compared to higher frequency implementations as less wideband design options like (active) filters [Reference Hu and Mouthaan11, Reference Hu and Mouthaan12, Reference Ma, Leenaerts and Mahmoudi14, Reference Garakoui, Klumperink, Nauta and van Vliet16, Reference Kim, Hong Kang, Hwang and Ahn18], artificial transmission lines (ATLs) [Reference Abbasi and Lee8, Reference Ma, Leenaerts and Mahmoudi9, Reference Cho, Song and Cressler19], and compact switches are available. In contrast, the mm-wave designs [Reference Karakuzulu, Eissa, Kissinger and Malignaggi20–Reference Maurette-Blasini, Kuliabin, Chartier and Quay22] use conventional transmission lines and area inefficient $\lambda/4$ transformed shunt switches. Paper [Reference Abbasi and Lee8] achieves a much higher area efficiency as series CMOS switches are used and $\lambda/4$ lines are mostly avoided. The general trend can be empirically approximated by a delay of one period per square millimeter.

Figure 8.

Delay range per core area of integrated TTD elements [Reference Koch, Probst, Breun and Weigel1, Reference Abbasi and Lee8–Reference Shin, Yom and Kim17, Reference Cho, Song and Cressler19–Reference Govind, Tapen and Apsel23, Reference Zolkov, Weiss, Madjar and Cohen25–Reference Shen, Zhang, Yang, He, Guo and Gao27] versus their maximum supported frequency and a trendline indicating one period per square millimeter.

Operational principles and realizations

TTD elements covering large time delays typically involve switches and constant delay elements as this technique offers low losses for large delays and well-predictable delay steps. Table 2 gives an overview of constant delay elements like lumped filters [Reference Hu and Mouthaan11, Reference Hu and Mouthaan12, Reference Ma, Leenaerts and Mahmoudi14, Reference Garakoui, Klumperink, Nauta and van Vliet16, Reference Kim, Hong Kang, Hwang and Ahn18] that are highly efficient regarding chip area per delay but are limited to low frequencies compared to artificial transmission lines (ATLs) [Reference Abbasi and Lee8, Reference Ma, Leenaerts and Mahmoudi9, Reference Cho, Song and Cressler19] or transmission lines (TLs) [Reference Koch, Probst, Breun and Weigel1, Reference Karakuzulu, Eissa, Kissinger and Malignaggi20–Reference Maurette-Blasini, Kuliabin, Chartier and Quay22]. Switching between different delays can be accomplished by selecting the desired tap of a delay chain [Reference Ma, Leenaerts and Mahmoudi9, Reference Ma, Leenaerts and Mahmoudi14, Reference Garakoui, Klumperink, Nauta and van Vliet16, Reference Kim, Hong Kang, Hwang and Ahn18], posing the problem of imperfect matching at higher frequencies, making techniques, e.g. as described by [Reference Ma, Leenaerts and Mahmoudi9] necessary. Another special case is the trombone architecture that incorporates a forward and reverse traveling signal line with switched amplifiers that select the point of return [Reference Hu and Mouthaan11, Reference Hu and Mouthaan12]. If switches are used instead of amplifiers, impedance matching at the point of return must be assured which requires a high impedance state of the remaining TLs. This can be achieved by shorting the lines $\lambda/4$ after the point of return [Reference Abbasi and Lee8]. Another switch-based architecture is bypassing of individual (binary weighted) delays using dual SPDT switches [Reference Cho, Song and Cressler19–Reference Maurette-Blasini, Kuliabin, Chartier and Quay22]. As series transistor switches are difficult to realize at very high frequencies, some millimeter-wave implementations use $\lambda/4$ transformed shunt switches [Reference Karakuzulu, Eissa, Kissinger and Malignaggi20–Reference Maurette-Blasini, Kuliabin, Chartier and Quay22]. To accommodate for the parasitic elements of switches, some designs integrate switch and delay element, resulting in self-switched all-pass networks [Reference Abbasi and Lee8, Reference Willms, Ouacha, de Boer and van Vliet10, Reference Hu and Mouthaan12]. Reflective type delay elements require directional couplers but allow delay selection by shorting the signal to ground or even employing offset shorts for better delay resolution [Reference Govind, Tapen and Apsel23].

Table 2.

Integrated TTD elements by operational principle

Most of the presented principles are not very suitable for small delay steps as the high amount of switches requires a large chip area and increases parasitic capacitance that limits the maximum frequency. Similar to a ring buffer, many sample and hold circuits can be used to temporarily save the input signal and delay the output signal [Reference Zolkov, Weiss, Madjar and Cohen25, Reference Shen, Zhang, Yang, He, Guo and Gao27]. However, to cover higher frequencies, the resolution of lumped filters and reflective delays can be improved by integrating digitally controlled capacitors [Reference Garakoui, Klumperink, Nauta and van Vliet16] or varactors [Reference Hu and Mouthaan12, Reference Ulusoy, Schleicher and Schumacher13, Reference Govind, Tapen and Apsel23]. The same technique is applicable to ATLs and TLs, but a trade-off between pole frequency, impedance matching, tuning range, and variation of the capacitor’s quality factor and therefore loss variation across delay setting has to be found, which is increasingly difficult at higher frequencies [Reference Ma, Leenaerts and Mahmoudi9, Reference Ma, Leenaerts and Mahmoudi14, Reference Woods, Valdes-Garcia, Ding and Rascoe15, Reference Shin, Yom and Kim17]. Some designs also incorporate tunable inductors to preserve impedance matching over delay [Reference Woods, Valdes-Garcia, Ding and Rascoe15]. A less intuitive approach is to exploit different propagation speeds in common and differential mode of coupled lines. By injecting an amplitude controlled copy of the signal in the second path, modes can be changed and therefore the delay of the line. This technique is limited in its maximum delay by power transfer and therefore gain variation over delay setting [Reference Lee and Valdes-Garcia26]. An alternative to high resolution TTD are conventional phase shifters with limited tuning range, combined with a coarse TTD element, causing only negligible beam squinting [Reference Mailloux3, Reference Steinweg, Carta and Ellinger21]. The delay interpolation principle employed in this work is similar to a vector phase shifter, but instead of a ${90}{^\circ}$ hybrid, a TL is used, which allows for continuous delay control by interpolation [Reference Koch, Probst, Breun and Weigel1].

Hierarchical beamforming systems

This section describes a concept for a completely time delay controlled array that can be realized using the delay interpolation principle. Because, according to (2), the required delay range increases linearly with array size, the hierarchical architecture shown in Fig. 11 is proposed to benefit from the typically higher delay ranges of baseband TTD elements. As continuously adjustable TTD elements are utilized, no grating lobes due to quantization or beam squinting are expected, yet some deterioration, e.g. due to gain variation or tuning non-linearity is expected.

Figure 11.

An eight-element linear antenna array controlled by a three-level hierarchical beamforming network.

The required element-to-element delay of a 1 mm-spaced antenna array for $\theta_0 = {45}{^\circ}$ in D-band is calculated by (1) as $\tau_0={2.35}$ ps and has to be available for controlling the two-element subarrays. Two cascaded TTD elements for subarray beamsteering in the RF domain are proposed to meet the required tuning range while reducing the loss at $B = {0.5}\,{}$ in comparison to a single element. As the distance and therefore also the required delay between the subarray ports is 6 times higher, a combination of baseband TTD and LO phase shifting becomes more attractive. For zero-IF systems, the highest frequency that the TTD element has to support is $\frac{BW}{2}$ instead of $f_\text{LO} + \frac{BW}{2}$ which increases the achievable delay range of delay interpolation TTD by a factor of ${5.6}\,{}$ for the D-band example. Due to the increased delay range of 7 ps for the continuous delay elements, a single fixed 7 ps delay element with crossover switch is sufficient for preserving continuous delay control. If the fixed delay element is switched to either side, the delay can be compensated by the continuous elements on the other side, yielding $\theta_0={0}{^\circ}$, or increased by the elements on the same side, which defines the maximum scan angle $\theta_\text{0,max}={45}{^\circ}$ since $6\tau_0\approx 2 \cdot {7}$ ps. For scanning the other half of space, the crossover switch has to be toggled. The use of baseband TTD appears further attractive because area efficiency may be increased by replacing spacious inductive matching networks with resistors due to higher gain and efficiency at lower frequencies. Depending on the chosen architecture, gain variation may also be improved by lower losses of long delay lines and switches.

The timed array's gain has been simulated for a cosine modeled element pattern, appropriately switched delay element and by using the transfer function of the delay interpolation TTD element (15) with B determined by (17) without applying further compensation. Figure 12 shows the element pattern together with the wide patterns of the subarrays and the narrower patterns of the overall eight-element array. The frequency dependent gain variation due to the RF TTD element becomes apparent for $B_\text{TTD,RF}={0.5}\,{}$ at $\theta_0={0}{^\circ}$ where significant deviation between element and subarray pattern can be seen, while at higher scan angles the RF TTD elements operate closer to the extreme settings where less losses occur. At $\theta_0= {20}{^\circ}$, gain variation of the baseband TTD elements cause a reduced gain of the array pattern compared to the subarrays’ pattern towards the band edges. The influence of gain variation on the array gain shows the need for hardware-based gain compensation or a control-based reduction, e.g. by avoiding the central control setting in a chain of cascaded delay interpolation TTD elements.

Figure 12.

Gain of a cosine modeled antenna (dotted) and the hierarchical timed array architecture for the two-element subarrays (dashed) and the complete eight-element array (solid) at scan angles θ ₀ of (a) ${0}{^\circ}$, (b) ${20}{^\circ}$, (c) ${30}{^\circ}$, and (d) ${45}{^\circ}$.

D-band implementation

Previously, we presented a D-band TTD design to evaluate the feasibility of the delay interpolation working principle, circuit non-idealities, and compensation techniques [Reference Koch, Probst, Breun and Weigel1]. The design as well as additional investigations regarding the non-idealities are presented in the following section. The implementation closely follows the topology shown in Fig. 9. As the output power at low frequencies and extreme delay settings is nearly equal to the sum of A and B, their sum is kept constant by splitting the input signal into parts A and B. For this purpose, the architecture of a conventional cascode current steering variable gain amplifier is slightly altered to realize an adjustable splitter, shown in Fig. 14(b), that keeps the overall power of both signals constant, but divides them into two weighted components. The ratio of both signals can be controlled by potentials c ₁ and c ₂, which are set by a differential current mode digital-to-analog converter (DAC). Ideally, the input conductance of the splitting stage is constant as it is $g_1 + g_2 = \frac{I_1}{V_T} + \frac{I_2}{V_T}$ with the sum of the collector currents $I_1 + I_2$ and the thermal voltage V_T being constant. However, high frequency designs commonly use small transistor sizes to reduce parasitic capacitance which increases undesired series resistance. If the splitting stage’s input admittance g _s is modeled by (20) using the transistors’ small signal conductances, an emitter series resistance $R_E = {9.6}\,{\Omega}$ and an RC network, representing parasitic coupling from emitter to collector, a non-constant input admittance is obtained as shown in Fig. 13(a). Good agreement between simulation and calculation at DC is observed, while at the center frequency of 145 GHz parasitic elements cause a higher deviation. Further, the ratio of g ₁, respectively g ₂, and the splitting stage’s simulated input node admittance $g_\text{n,sim}$ is used to estimate phase errors introduced by the power splitter. Figure 13(b) compares them with the simulated S-parameters of the complete splitter circuit. In the regions of high gain, a good accordance is observed while at low gain the phase is sensitive to the transistors’ isolation properties, which are only coarsely modeled by the simple RC network

Figure 13.

Simulated (solid) and calculated (dashed) (a) splitting stage input admittance g _s at DC and center frequency, individual emitter admittances g ₁, g ₂, (b) simulated phase of the complete splitter circuit S ₂₁, S ₃₁ (right axis) and phase from the ratio of calculated g ₁, g ₂ and simulated admittance of the splitting stages input node g_n.

Figure 14.

Simplified schematics of (a) the summation circuit and (b) the adjustable splitter with control network.

(19)\begin{align} g_i = \frac{1}{R_E + \frac{V_T}{I_i}} + \frac{1}{{60}\,{\Omega} + \frac{1}{j \omega {7.6}\,{fF}}} \end{align}

(20)\begin{align} g_s &= g_1 + g_2. \end{align}

The splitter’s matching is realized with coupled inductors at the input and transformers at the output, both optimized for a center frequency of 145 GHz.

Two differential TLs with a delay difference of 1.78 ps are used as delay element which provide a well-predictable delay and simplified routing. As the length difference of the TLs reaches ${90}{^\circ}$, imperfect matching and impedance transformation along the delay line cause asymmetry in the amplitude response. The signal-flow path shown in Fig. 15(a) is used to quantify the effect of reflections at the splitter’s outputs and the summation circuit’s inputs as well as finite isolation between the summation circuit’s inputs. As a result, (21) shows altered gain of the inphase and delayed component. Assuming an ideal splitter, Fig. 15(b) shows that 10 dB matching and isolation ($\Gamma_1=\Gamma_2=0.316, i=j \cdot 0.316$) cause up to 2.1 dB additional insertion loss, depending on the chosen delay. However, coefficients obtained from simulation of the realized circuit yield only 0.73 dB loss. It is also shown that inserting the splitter’s amplitude and phase response as parameters A and B gives good accordance with the simulated results of the complete TTD circuit with lossless delay lines. The TTD circuit incorporates an active summation circuit shown in Fig. 14(a) which has higher isolation than a simple resistive power combiner and allows to individually adjust the gain of the two inputs for error correction

Figure 15.

(a) Signal-flow graph considering reflections at the splitter’s outputs (Γ₁), the summation circuit’s inputs (Γ₂), and isolation of the summation circuit (i). (b) Simulated gain at 140 GHz of the TTD circuit with lossless delay lines (solid, right axis), calculated gain using simulated reflection parameters and isolation (dashed), calculated gain without reflections and infinite isolation (dotted), calculated gain with 10 dB matching and 10 dB isolation (dash-dotted) for an ideal splitter and different splitter bias currents, and (c) phase responses for the same cases.

(21)\begin{align} G &= \frac{\sqrt{1-|\Gamma_1|^2} \sqrt{1-|\Gamma_2|^2-|i|^2}}{1+\Gamma_1^2 i^2 - \Gamma_1^2 \Gamma_2^2} \big( A \left(1 + \Gamma_1 (\Gamma_2 - i) \right) \nonumber \\ & \quad + B e^{-j\frac{\pi}{2}} \left( 1-\Gamma_1 (\Gamma_2 - i) \right) \big). \end{align}

The demonstrator chip including calibration structures is shown in Fig. 16. It has been manufactured in IHP’s SG13G2 130 nm BiCMOS technology that has an f _t/f _max of 350 GHz/450 GHz. The steering control and all three bias currents are individually controlled by on-chip DACs and can be optimized to compensate gain variation.

Figure 16.

Micrograph of the demonstrator with fabricated D-band TTD element occupying 0.53 ×0.3 mm².

Measurement results for different bias currents of splitter, summation amplifiers, as well as the delay control byte have been obtained by on-chip measurements using a Keysight PNA-X, VDI VNAX frequency extenders, and a custom USB to serial peripheral interface adapter. Figure 17(a) shows gain, delay, and gain variation for a DC current of 6.1 mA for each amplifier. Although a gain of approximately 10 dB is achieved, gain variation suffers from asymmetry over delay setting, having the lowest gain at settings 125–190. A reduction of operating point current to 2.2 mA for the splitter and 4 mA for each summation input yields the results of Fig. 17(b) that show better symmetry but also reduced gain of 1.6 dB and a 3 dB bandwidth from 130 GHz to 156 GHz. Relative phase delay shows a tuning range of 1.63 ps and a good agreement with the simulated curves, yielding a Root mean square (RMS)delay error of 48 fs. The RMS delay error is derived from the shown measurement curves using the simulated delay, averaged over the TTD element's bandwidth, as reference. Within the bandwidth, gain differs between the different delay settings by maximally 2.8 dB and shows an RMS error of 1.0 dB. To reduce gain variation, a delay dependent biasing scheme is used. The splitter is set to 1.7 mA and the summation stages of long and short line to 3.6 mA and 2.2 mA. The currents of the summation stages are increased by a quadratic boost factor up to a maximum of 7.6 mA, respectively 4.8 mA, at delay setting 127. The results in Fig. 17(c) show a reduction of maximum gain error to 0.5 dB and an RMS gain error of 0.2 dB while gain is slightly reduced to 0 dB and the delay range is now 1.75 ps.

Figure 17.

Measured (solid) and simulated (dashed) gain, relative delay, and relative gain of the D-band TTD element for (a) an overall constant bias current of 19.3 mA, (b) 10.9 mA, and (c) compensation of gain variation by a quadratic boost in bias current, yielding 9–15 mA current consumption.

Table 3 gives a comparison of the uncompensated and compensated TTD element with other sub-THz TTD elements and wideband TTD elements with high delay range. In contrast to the passive implementation of switch based TTD implementations [Reference Abbasi and Lee8, Reference Karakuzulu, Eissa, Kissinger and Malignaggi20], the presented TTD element does not have high losses but is more limited in terms of bandwidth due to the amplifiers. The employed working principle is limited to approximately ${90}{^\circ}$ delay range at its highest frequency and therefore has a smaller tuning range, but it does offer high delay resolution that is only limited by the integrated 8-bit DAC, although higher linearity would be desirable that is found to be currently limited by the parasitic emitter resistance of the splitting stage’s transistors and imperfect matching of the delay lines. Still, a good accordance between simulation and measurement is found resulting in an RMS delay error of 44 fs. A combination of the presented principle with a switched topology appears appealing as area requirements of [Reference Karakuzulu, Eissa, Kissinger and Malignaggi20] and gain variation of [Reference Abbasi and Lee8] seem to be further improvable without introducing phased subarrays that cause grating lobes. As better linearity and gain variation are expected with wider transistors and lower delay to signal period ratio $\tau/T$, the presented concept is also a possible candidate for continuous and calibration free baseband TTD elements, that are currently realized using varactors [Reference Ma, Leenaerts and Mahmoudi9, Reference Hu and Mouthaan12].

Table 3.

Uncompensated and compensated performance of the D-band TTD element in comparison with TTD elements above 100 GHz and wideband TTD elements with high delay range.

^a Only over limited BW;

^b uncompensated;

^c extracted from graph.