This chapter presents a comprehensive overview of electrostatic discharge (ESD) characterization methodologies essential for robust integrated circuit (IC) protection design. It begins by detailing standard ESD test models – human body model (HBM), charged device model (CDM),, and machine model (MM) – emphasizing their circuit representations, waveform characteristics, and relevance to real-world failure mechanisms. The influence of IC package types on CDM performance is analyzed, highlighting the need for accurate modeling and simulation. The chapter then discusses electrical overstress (EOS),, system-level ESD standards like International Electrotechnical Commission (IEC) 61000-4-2 and International Organization for Standards (ISO) 10605, and discharge events including cable discharge event (CDE) and charged board event (CBE). A variety of diagnostic tools such as transmission line pulse (TLP), very fast TLP (VfTLP), capacitively coupled TLP (CCTLP), and human metal model (HMM) are reviewed for their role in characterizing ESD robustness. It explores the evolution of test methods, the relevance of failure analysis, and the industry’s push toward revised ESD qualification standards. The chapter in the end emphasizes on the system efficient ESD Design (SEED) as a viable strategy for addressing the demands of advanced technologies and high-speed system interfaces.