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This paper describes a modification of the power set construction for the transformation of self-verifying nondeterministic finite automata to deterministic ones. Using a set counting argument, the upper bound for this transformation can be lowered from $2^n$ to $O(\frac{2^n}{\sqrt{n}}).$
We present a compositional programme logic for call-by-value imperative higher-order functions with general forms of aliasing, which can arise from the use of reference names as function parameters, return values, content of references and parts of data structures. The programme logic extends our earlier logic for alias-free imperative higher-order functions with new operators which serve as building blocks for clean structural reasoning about programms and data structures in the presence of aliasing. This has been an open issue since the pioneering work by Cartwright–Oppen and Morris twenty-five years ago. We illustrate usage of the logic for description and reasoning through concrete examples including a higher-order polymorphic Quicksort. The logical status of the new operators is clarified by translating them into (in)equalities of reference names.
We consider the distribution of the value of the optimal k-assignment in an m × n matrix, where the entries are independent exponential random variables with arbitrary rates. We give closed formulas for both the Laplace transform of this random variable and for its expected value under the condition that there is a zero-cost (k − 1)-assignment.
Une substitution est un morphisme de monoïdes libres :chaque lettre a pour image un mot, etl'image d'un mot est laconcaténation des images de ses lettres.Cet article introduit unegénéralisation de la notion de substitution,où l'image d'une lettre n'est plus un mot mais un motif, c'est-à-direun “mot à trous”, l'image d'un mot étant obtenue en raccordant lesmotifs correspondant à chacune de ses lettres à l'aide de règleslocales. On caractérisecomplètement les substitutions par des motifs qui sontdéfinies sur toute suite biinfinie, et on explique comment lesconstruire. On montre que toutesuite biinfinie qui est point fixe d'une substitution par des motifsest substitutive, c'est-à-dire est l'image, par un morphisme lettre àlettre, d'un point fixe de substitution (au sens usuel).
We study some arithmetical and combinatorial properties ofβ-integers for β being the larger root of the equationx2 = mx - n,m,n ∈ ℵ, m ≥ n +2 ≥ 3. We determine withthe accuracy of ± 1 the maximal number of β-fractionalpositions, which may arise as a result of addition of twoβ-integers. For the infinite word uβ> coding distancesbetween the consecutive β-integers, we determine preciselyalso the balance. The word uβ> is the only fixed point of themorphism A → Am-1B and B → Am-n-1B. In the case n = 1,the corresponding infinite word uβ> is sturmian, and,therefore, 1-balanced. On the simplest non-sturmian example withn≥ 2, we illustrate how closely the balance and thearithmetical properties of β-integers are related.
We explore the borderline between decidability and undecidability of the following question: “Let C be a class of codes. Given a machine ${\mathfrak{M}}$ of type X, is it decidable whether the language $L({{\mathfrak{M}}})$ lies in C or not?” for codes in general, ω-codes, codes of finite and bounded deciphering delay, prefix, suffix and bi(pre)fix codes, and for finite automata equipped with different versions of push-down stores and counters.
This paper has two parts. In the first part we consider a simple Markov chain for d-regular graphs on n vertices, where d = d(n) may grow with n. We show that the mixing time of this Markov chain is bounded above by a polynomial in n and d. In the second part of the paper, a related Markov chain for d-regular graphs on a varying number of vertices is introduced, for even constant d. This is a model for a certain peer-to-peer network. We prove that the related chain has mixing time which is bounded above by a polynomial in N, the expected number of vertices, provided certain assumptions are met about the rate of arrival and departure of vertices.
A black hole is a highly harmful stationary process residing in a node of a network and destroying all mobile agents visiting the node, without leaving any trace. We consider the task of locating a black hole in a (partially) synchronous tree network, assuming an upper bound on the time of any edge traversal by an agent. The minimum number of agents capable of identifying a black hole is two. For a given tree and given starting node we are interested in the fastest-possible black hole search by two agents. For arbitrary trees we give a 5/3-approximation algorithm for this problem. We give optimal black hole search algorithms for two ‘extreme’ classes of trees: the class of lines and the class of trees in which any internal node (including the root which is the starting node) has at least two children.
We extend the 0-approximation of sensing actions and incomplete information in Son and Baral (2001) to action theories with static causal laws and prove its soundness with respect to the possible world semantics. We also show that the conditional planning problem with respect to this approximation is NP-complete. We then present an answer set programming based conditional planner, called ASCP, that is capable of generating both conformant plans and conditional plans in the presence of sensing actions, incomplete information about the initial state, and static causal laws. We prove the correctness of our implementation and argue that our planner is sound and complete with respect to the proposed approximation. Finally, we present experimental results comparing ASCP to other planners.
Existing languages provide good support for typeful programming of stand-alone programs. In a distributed system, however, there may be interaction between multiple instances of many distinct programs, sharing some (but not necessarily all) of their module structure, and with some instances rebuilt with new versions of certain modules as time goes on. In this paper, we discuss programming-language support for such systems, focussing on their typing and naming issues. We describe an experimental language, Acute, which extends an ML core to support distributed development, deployment, and execution, allowing type-safe interaction between separately built programs. The main features are (1) type-safe marshalling of arbitrary values; (2) type names that are generated (freshly and by hashing) to ensure that type equality tests suffice to protect the invariants of abstract types, across the entire distributed system; (3) expression-level names generated to ensure that name equality tests suffice for type safety of associated values, for example, values carried on named channels; (4) controlled dynamic rebinding of marshalled values to local resources; and (5) thunkification of threads and mutexes to support computation mobility. These features are a large part of what is needed for typeful distributed programming. They are a relatively lightweight extension of ML, should be efficiently implementable, and are expressive enough to enable a wide variety of distributed infrastructure layers to be written as simple library code above the byte-string network and persistent store APIs. This disentangles the language run-time from communication intricacies. This paper highlights the main design choices in Acute. It is supported by a full language definition (of typing, compilation, and operational semantics), by a prototype implementation, and by example distribution libraries.
Every smart-card vendor has its implementation of the ISO 7816 file structure and application selection process: these form the vendor's native operating system and, as we have seen in Chapter 6, they can be used to create a multi-application card scheme.
To gain the full benefits of portability, a high-level language and post-issuance downloading of applications, you need a multi-application operating system like JavaCard or Multos. But there are several operating systems that sit between these two extremes, and which may offer advantages in some situations.
IBM MFC
IBM developed its first multi-function card (MFC) 1 in the early 1990s. It has since been developed to extend the cryptographic support and add new features. One of its most important features, however, is the ability to support applications in E2PROM, which can be updated or downloaded after the initial issuance, using a scripting protocol.
IBM stopped supplying smart cards directly in 1999, but it has licensed the MFC to several manufacturers, and also develops tailored versions for specific schemes. It is now used by the French multi-application payment and e-purse card Monéo 2.
Advantis
Spanish card technology and systems supplier SERMEPA developed its ‘TIBC’ operating system in 1994 in order to run the ‘Visa Cash’ electronic purse product; TIBC was licensed to several card manufacturers and is still widely used in Spain and Latin America.
This chapter covers the key features of a smart card, its manufacturing process and the components of a smart-card system. It can be skipped by those who are already familiar with the technology and whose main interest is in advanced card types, and in particular in combining applications within a single card.
Appendix B also lists some further reading on smart-card technology in general.
What is a smart card?
Common features
A smart card is a card incorporating one or more integrated circuits within its thickness (see Figure 3.1). Smart cards are also often called chip cards or integrated circuit (IC) cards – these terms are interchangeable.
As we will see, the terms cover many cards that are not really ‘smart’ in the sense of being programmable, but the smartness comes from the way they are used as a part of a system.
Most smart cards meet the ISO 7810 standard (bank card size and thickness), but there are other standard card shapes, such as the ID-000 shape used by mobile telephone SIM cards. And some devices known as smart cards are not card-shaped at all – although this does raise a number of issues, as we will see in Chapter 6.
There are two main categories of smart cards, usually characterised as memory and microprocessor (or microcontroller) cards. The name microcontroller is technically more accurate since the chip includes memory, the serial interface and, possibly, more than one processor.
How do we know this to be the case? Well, if we look at the landscape of a typical industry sector, we see in smart cards the same characteristics we would witness in any other established and mature market.
For instance, companies have been created and thrive financially, based solely on the technology itself. These companies compete fiercely for a market share and brand leadership. Aggressive actions, such as mergers and acquisitions, and rigorous oversight of intellectual property rights are commonplace in the quest to increase both the industry and shareholder value. Dedicated industry analysts have built careers by following market movements and advances in the technology, and by prognosticating its future potential.
Trade shows and events have been established in every region of the world, dedicated to the exhibition of the technology and the sharing of information and industry best practices. These highly specialised gatherings not only showcase the latest in smart-card technology, but carefully articulate its relevance to critical sectors such as government, financial, retail, transit, healthcare and mobile telecommunications.
Industry associations have emerged to develop standards for smart cards and the applications that depend on the technology. In addition to developing standards, these birds-of-a-feather organisations have become valuable forums for information exchange between technology providers and end-user communities.
Magazines, periodicals, newsletters and websites cater exclusively to the smart-card industry. At the time of writing, a Google search on ‘smart cards’ resulted in 92 500 000 possible sites to explore.
The basic structure of a reader for contact cards was described in Chapter 3. This chapter considers the specific requirements of different sectors and of multi-application cards.
Reader type
In Chapter 3 we saw that readers may be manual or motorised, partial or full insertion, chip only or hybrid.
Motorised readers have specific advantages in multi-application environments too: the terminal can execute both ‘warm’ and ‘cold’ resets (see Chapter 8), allowing it to switch between applications without giving potentially confusing messages to the user or card-holder.
Many smart cards carry a magnetic stripe as well. This can be read when the card is inserted or when it is withdrawn; the former has advantages if some form of fallback is required, but reading a magnetic stripe on entry is often less smooth than reading on exit, and so gives slightly lower success rates. In retail environments where reliable reading of both chip and magnetic stripe cards is very important, special readers have been developed (see Figure 7.1) that combine a long reading slot for swiping with a ‘park’ position for reading the chip.
Contact readers must also have limit switches or other methods for detecting when a card is in place; these are used not only for powering up the card but also for detecting when a card has been inserted wrongly or not removed at the end of the transaction; in these cases it is often desirable for the terminal to emit a warning tone or signal.
It will be clear from the rest of this book that the availability of technology is no longer a limiting factor preventing the deployment of multi-application smart-card schemes. However, further technology developments will continue to appear and some of these will be distinctly helpful by allowing a wider range of applications, or by making existing applications work better or at lower cost.
Microcontrollers
At the chip level, semiconductor technology as a whole continues to advance in line with Moore's Law: doubling the number of gates per chip every eighteen months. In the case of microcontroller chips, the 0.12–0.15 μm technologies that are regarded as leading-edge in 2006 are believed to be close to the limit for E2PROM; however, flash memory is being used to grow total memory sizes into the megabyte range, and this technology will be used increasingly in combination with E2PROM to provide the memory sizes required by the telecommunications industry today, and probably for multi-application cards in the near future.
In 2000, I forecast that smart-card microcontrollers would be using 0.1 μm processes by 2005; this turns out to have been optimistic, but this level is now regularly used for DRAM products and should be achievable by 2007 for microcontrollers, moving to 0.07 μm or less by 2010.
Memory sizes for microprocessor cards, currently mostly in the range 4–128 kB, are likely to rise over the next few years to 32 kB–8 MB, with a wider range of combinations of memory types, perhaps configurable at a relatively late stage in the manufacturing process.