The ever-increasing use of smart phone devices, multimedia applications, and social networking, along with the demand for higher data rates, ubiquitous coverage, and better quality of service, pose new challenges to the traditional mobile wireless network paradigm that depends on macro cells for service delivery. Small cell networks (SCNs) have emerged as an attractive paradigm and hold great promise for future wireless communication systems (5G systems). SCNs encompass a broad variety of cell types, such as micro, pico, and femto cells, as well as advanced wireless relays, and distributed antenna systems. SCNs co-exist with the macro cellular network and bring the network closer to the user equipment. SCNs require low power, incur low cost, and provide increased spatial reuse. Data traffic offloading eases the load on the expensive macro cells with significant savings expected to the network operators using small cells.

As the demand for increased bandwidth rages on, SCNs emerged in dense urban areas mainly to provide coverage and capacity. They have now gained momentum and are expected to dominate in the coming years, with the rollout in large scale – either planned or in ad-hoc manner – and the development of 5G systems with many small cell components. Already, the number of “small cells” in the world exceeds the total number of traditional mobile base stations. SCNs are also envisioned to pave the way for new services. However, there are many challenges in the design and deployment of small cell networks, which have to be addressed in order to be technically and commercially successful. This book provides various concepts in the design, analysis, optimization, and deployment of small cell networks, using a treatment approach suitable for pedagogical and practical purposes.

This book is an excellent source for understanding small cell network concepts, associated problems, and potential solutions in next-generation wireless networks. It covers from fundamentals to advanced topics, deployment issues, environmental concerns, optimized solutions, and standards activities in emerging small cell networks. New trends, challenges, and research results are also provided. Written by leading experts in the field from academia and industry around the world, it is a valuable resource dealing with both the important, core, and specialized issues in these areas. It offers a wide coverage of topics, while balancing the treatment to suit the needs of first-time learners of the concepts and specialists in the field.

We disseminate a set of small cells' field trial experiments conducted at 2.6 GHz and focused on coverage/capacity within multi-floor office buildings. LTE pico cells deployed indoors as well as LTE small cells deployed outdoors are considered. The latter rely on small emission power levels coupled with intelligent ways of generating transmission beams with various directivity levels by means of adaptive antenna arrays. Furthermore, we introduce an analytical three-dimensional (3D) performance prediction framework, which we calibrate and validate against field measurements. The framework provides detailed performance levels at any point of interest within a building; it allows us to determine the minimum number of small cells required to deliver desirable coverage and capacity levels, their most desirable location subject to deployment constraints, transmission power levels, antenna characteristics (beam shapes), and antenna orientation (azimuth, tilt) to serve a targeted geographical area. In addition, we disseminate specialized solutions for LTE small cells’ deployment within hotspot traffic venues, such as stadiums, through design and deployment feasibility analysis.

Introduction

Small cells are low-cost, low-power base stations designed to improve coverage and capacity of wireless networks. By deploying small cells on top and in complement to the traditional macro cellular networks, operators are in a much better position to provide the end users with a more uniform and improved quality of experience (QoE). Small cells’ deployment is subject to service delivery requirements, as well as to the actual constraints specific to the targeted areas. For a good uniformity of service, in populated areas where the presence of buildings is the main reason for significant radio signal attenuation, small cells may need to be closely spaced, e.g., within a couple of hundred meters from each other. Naturally, the performance of small cells is highly dependent on environment-specific characteristics, such as the materials used for building construction, their specific propagation properties, and the surroundings. It is particularly important to have a proper characterization of an environment where small cells are deployed.

This chapter focuses on in-building performance and feasibility of LTE small cells through measurements, taking as reference both outdoor small cell and indoor pico cell deployments. We created scenarios where wireless connectivity within a target building is offered either by small cells located on the exterior of other buildings (small cells with outdoor characteristics) or simply by small cells located within the target building (pico cells with indoor characteristics).

Functional programming – the use and evaluation of functions as a programming paradigm – has a long and productive history in the world of programming languages. Lisp came about in the 1950s in the search for a convenient language to represent mathematical concepts in programs, borrowing from the lambda calculus of the logician Alonzo Church. More recent languages have in turn embraced many aspects of Lisp – in addition to Lisp's offspring such as Scheme and haskell, you will find elements of functional constructs in Java, Python, Ruby, and Perl. Mathematicaitself has clear bloodlines to Lisp, including the ability to operate on data structures such as lists as single objects and in its representation of mathematical properties through rules.

Mathematica functions, unlike those in many other languages, are considered “first-class” objects, meaning that they can be used as arguments to other functions, they can be returned as values, and they can be part of many other kinds of data objects such as arrays. In addition, you can create and use functions at runtime, that is, when you evaluate an expression. This functionalstyle of programming distinguishes Mathematicafrom traditional procedural languages like C and Fortran. Facility with functional programming is therefore essential for taking full advantage of the Mathematica language to solve your computational tasks.

We start with some of the most useful functional programming constructs – higher-order functions such as Map, Apply, Thread, Select, and Outer. We then introduce iteration, a mechanism by which the output of one computation is fed as input into the next.

Small cell networks

The tremendous increase of bandwidth-craving mobile applications (e.g., video streaming, video chatting, and online gaming) has posed enormous challenges to the design of future wireless networks. Deploying small cells (e.g., pico, micro, and femto) has been shown to be an efficient and cost-effective solution to support this constantly rising demand since the smaller cell size can provide higher link quality and more efficient spatial reuse [1]. Small cells could also deliver some other benefits such as offloading the macro network traffic, providing service to coverage holes and regions with poor signal reception (e.g., macro cell edges). Following this trend, the evolving 5G networks [2] are expected to be composed of hundreds of interconnected heterogeneous small cells.

Figure 11.1 gives an illustration of a heterogeneous network (HetNet) where a macro cell is underlaid with different types of small cells. Different from the cautiously planned traditional network, the architecture of a HetNet is more random and unpredictable due to the increased density of small cells and their impromptu way of deployment. In this case, the manual intervention and centralized control used in traditional network management will be highly inefficient, time consuming, and expensive, and therefore will be not applicable for dense heterogeneous small cell networks. Instead, self-organization has been proposed as an essential feature for future small cell networks [3, 4].

The motivations for enabling self-organization in small cell networks are explained below.

1. • Numerous network devices with different characteristics are expected to be interconnected in future wireless networks. Also, these devices are expected to have “plug and play” capability. Therefore the initial pre-operational configuration has to be done with minimum expertise involvement.

2. • With the emergence of small cells, the spatio-temporal dynamics of the networks has become more unpredictable than legacy systems due to the unplanned nature of small cell deployment. Therefore intelligent adaptation of the network nodes is necessary. That is, the self-organizing small cells need to learn from the environment and adapt with the network dynamics to achieve the desired performance.

SYSTEM DESIGN PROCESS

The design of a system involves the following steps.

Specification The most important step in designing any system is deciding – and clearly specifying in writing – what you are going to build. We discuss specifications in more detail in Section 21.2.

Partitioning Once the system has been specified, the main task in system design is dividing the system into manageable subsystems or modules. This is a process of divide and conquer. The overall system is divided into subsystems that can then be designed (conquered) separately. At each stage, the subsystems should be specified to the same level of detail as the overall system was during our first step. As described in Section 21.3, we can partition a system by state, task, or interface.

Interface specification It is particularly important that the interfaces between subsystems be described in detail. With good interface specifications, individual modules can be developed and verified independently. When possible, interfaces should be independent of module internals – allowing modules to be modified without affecting the interface, or the design of neighboring modules.

Timing design Early in the design of a system, it is important to describe the timing and sequencing of operations. In particular, as work flows between modules, the sequencing of which module does a particular task on a particular cycle must be worked out to ensure that the right data come together at the correct place and time. This timing design also drives the performance tuning step described below.

Programming with Mathematica

In its brief history, the world of programming has undergone a remarkable evolution. Those of us old enough to remember boxes of punch cards and batch jobs couldn't be happier about some of these changes. One could argue that the limitations, physical and conceptual,of the early programming environments helped to focus that world in a very singular manner. Eventually, efforts to overcome those limitations led to a very visible and broad transformation of the world of computer programming. We now have a plethora of languages, paradigms, and environments to choose from. At times this embarrassment of riches can be a bit overwhelming, but I think most would agree that we are fortunate to have such variety in programming languages with which to do our work.

I learned about Mathematica as I suspect many people have – after using several languages over the years, a colleague introduced me to a new and very different tool, Mathematica. I soon realized that it was going to help me in my work in ways that previous languages could not. Perhaps the most notable feature was how quickly I could translate the statement of a problem to a working program. This was no doubt due to having a functional style of programming at my fingertips but also being able to think in terms of rules and patterns seemed to fit well with my background in mathematics.

Well, Mathematica is no longer a young up-start in the programming world. It has been around now for over 25 years, making it, if not an elder statesman, certainly a mature and familiar player. And one that is used by people in fields as varied as linguistics, bioinformatics, engineering, and information theory. Like myself, many people are first introduced to it in an academic setting. Many more are introduced through a colleague at work. Still others have seen it mentioned in various media and are curious as to what it is all about. After using it to do basic or more advanced computation, most users soon find the need to extend the default set of tools that come with Mathematica.Programming is the ticket.

So what makes Mathematica such a useful programming tool? First, it is a well-designed language, one whose internal logic will be quite apparent as you get to know it.

This book is intended to teach an undergraduate student to understand and design digital systems. It teaches the skills needed for current industrial digital system design using a hardware description language (VHDL) and modern CAD tools. Particular attention is paid to systemlevel issues, including factoring and partitioning digital systems, interface design, and interface timing. Topics needed for a deep understanding of digital circuits, such as timing analysis, metastability, and synchronization, are also covered. Of course, we cover the manual design of combinational and sequential logic circuits. However, we do not dwell on these topics because there is far more to digital system design than designing such simple modules.

Upon completion of a course using this book, students should be prepared to practice digital design in industry. They will lack experience, but they will have all of the tools they need for contemporary practice of this noble art. The experience will come with time.

This book has grown out of more than 25 years of teaching digital design to undergraduates (CS181 at Caltech, 6.004 at MIT, EE121 and EE108A at Stanford). It is also motivated by 35 years of experience designing digital systems in industry (Bell Labs, Digital Equipment, Cray, Avici, Velio Communications, Stream Processors, and NVIDIA). It combines these two experiences to teach what students need to know to function in industry in a manner that has been proven to work on generations of students. The VHDL guide in Appendix B is informed by nearly a decade of teaching VHDL to undergraduates at UBC (EECE 353 and EECE 259).

We wrote this book because we were unable to find a book that covered the system-level aspects of digital design. The vast majority of textbooks on this topic teach the manual design of combinational and sequential logic circuits and stop. While most texts today use a hardware description language, the vast majority teach a TTL-esque design style that, while appropriate in the era of 7400 quad NAND gate parts (the 1970s), does not prepare a student to work on the design of a three-billion-transistor GPU. Today's students need to understand how to factor a state machine, partition a design, and construct an interface with correct timing. We cover these topics in a simple way that conveys insight without getting bogged down in details.

MEMORY PRIMITIVES

The vast majority of all memories in digital systems are implemented from two basic primitives: on-chip SRAM arrays and external SDDR DRAM chips. Here we will consider these memory primitives as black boxes, discussing their properties and how to interface to them. It is beyond the scope of this book to look inside the box and study their implementation.

SRAM arrays

On-chip SRAM arrays are useful for building small, fast, dedicated memories integrated near the logic that produces and consumes the data they store. While the total capacity of the SRAM that can be realized on one chip (about 400 Mb) is small compared with a single 4 Gb DRAM chip, these arrays can be accessed in a single clock cycle, compared with 25 cycles or more for a DRAM access.

BASIC PRINCIPLES

We start with a few basic principles on which our VHDL style is based. The style presented is essentially a VHDL-2008 equivalent to a set of Verilog style guidelines based upon our experience over many years of teaching students digital design and managing design projects in industry combined with nearly a decade of experience teaching earlier versions of VHDL.

Know where your state is Every bit of state in your design should be explicitly declared. In our style, all state is in explicit flip-flop or register components, and all other portions are purely combinational. This approach avoids a host of problems that arise when writing sequential statements directly within an “if rising\_edge(clk) then” statement inside a process. It also makes it much easier to detect inferred latches that occur when not all signals are assigned in all branches of a conditional statement.

Understand what your design entities will synthesize to When you write a design entity, you should have a good idea what logic will be generated. If your design entity is described structurally, wiring together other components, the outcome is very predictable. Small behavioral design entities and arithmetic blocks are also very predictable.

DESIGN VERIFICATION

Simulation is the primary tool used to verify that a design meets its specification. The design is simulated using a number of tests that provide stimulus to the unit being tested and check that the design produces correct outputs. The VHDL testbenches we have seen throughout this book are examples of such tests.

Verification coverage

The verification challenge amounts to ensuring that the set of test patterns, the test suite, written to verify a design is complete. We measure the degree of completion of a test suite by its coverage of the specification and of the implementation. We typically insist on 100% coverage of both specification features and implementation lines or edges to consider the design verified.

The specification coverage of a set of tests is measured by determining the fraction of features in the specification that are exercised and checked by the tests. For example, suppose you have developed a digital clock chip that includes a day/date and an alarm function. Table 20.1 gives a partial list of features to be tested. Even for something as simple as a digital clock, the list of features can easily run into the hundreds. For a complex chip it is not unusual to have 105 or more features. Each test verifies one or more features. As tests are written, the features covered by each test are checked off.