In a synchronous circuit, the clock signal synchronizes the operation of various circuit elements. For deterministic circuit operation, certain timing constraints must be satisfied between the data signal relative to the clock signal. If these constraints are violated then the circuit can go into a metastable state or an invalid state. Therefore, we need to verify that these constraints are indeed satisfied in a synchronous circuit [1–4]. We use static timing analysis (STA) for this purpose. The simplicity and computational efficiency of STA have made synchronous design methodology the de facto standard for complicated digital circuits.

An STA tool verifies that a given synchronous circuit operates deterministically and remains in a valid state for a given frequency even in the worst-case scenario. Note that the purpose of STA is not to find a frequency at which a circuit can operate. Its purpose is just to ascertain whether a given circuit can safely operate at a given frequency and operating conditions. Therefore, STA needs to examine only the worst-case behavior for the circuit. It greatly simplifies the problem for an STA tool. It need not evaluate the circuit response to all possible input stimuli because most of them do not contribute to the worst-case behavior. Hence, STA employs methods that do not require applying stimuli and observing their dynamic responses. In this sense, STA is a static verification technique. It employs efficient stimuli-independent techniques to examine the worst-case behavior of a circuit.

In this chapter, we first describe the expected behavior of a synchronous circuit. Then, we derive the timing constraints that must be met to achieve this synchronous behavior. Next, we explain the techniques employed by the STA tools to ensure that these constraints are satisfied. We also highlight the assumptions used by the STA tools and point out the merits and demerits of these assumptions. Finally, we explain some of the popular techniques to account for variations in STA.

The power–performance trade-off has now become a key ingredient in VLSI design flows. The increased power dissipation in integrated circuits (ICs) and the ubiquitous use of battery-powered devices have made incorporating power-saving techniques essential to the design flows. Since powersaving strategies are more effective early in the flow, we adopt low-power design methodologies right from the pre-RTL stages. Subsequently, the power-related tasks permeate throughout the design flow.

We can broadly classify the power-related tasks as: power analysis and power-driven optimizations. In this chapter, we will explain power analysis methods. In the next chapter (“Powerdriven optimization”), we will discuss power optimization techniques.

COMPONENTS OF POWER DISSIPATION

There are two components of power dissipation in a CMOS circuit: dynamic power dissipation and static power dissipation. The dynamic power dissipation occurs when a circuit performs computation actively, i.e., a signal or the output of a logic gate changes its value. The static power dissipation occurs when the circuit is powered on (supply voltages are applied), but it does not perform active computation. Let us understand these components of power dissipation in more detail.

Dynamic Power Dissipation

Consider a CMOS inverter II, shown in Figure 18.1(a). The output pin drives the input of other logic gates through wires. The total load due to these M input pins is CI = ΣM i=1 Ci, where Ci is the capacitance of the ith input pin. The wires offer load capacitance Cw. Additionally, the driving pin Z has parasitic capacitances Cd due to the drain diffusion regions of the transistors. Thus, an output pin of a CMOS logic gate has total load capacitance:

We can use the circuit shown in Figure 18.1(b) for understanding dynamic power dissipation. Assume that the inverter undergoes a transition from 0→1 or 1→0. These transitions lead to power dissipation due to switching of capacitors and due to drawing short-circuit current from the power supply. We discuss these components of power dissipation in the following paragraphs.

Earlier, we discussed dividing the RTL to GDS implementation flow into two parts: logic synthesis and physical design. In this part of the book, we will discuss logic synthesis. In Part IV, we will discuss physical design.

Logic design involves transforming a high-level functional description to a netlist of standard cells and macros. It takes a design from the functional domain to the structural domain. The primary task of logic design is to decide the logic elements that will deliver the required functionality. Additionally, we need to ensure that the design metrics such as area, performance, power, and testability meet the given requirements.

To ensure that the logic design meets the above requirements, we interleave implementation and verification tasks in a design flow. We have arranged implementation and verification-related chapters similarly. However, note that we carry out some of the verification tasks, such as combinational equivalence checking, timing analysis, and power analysis, multiple times in a design flow.

We will explain implementation of the logical design in Chapter 8 (“Modeling Hardware using Verilog”), Chapter 10 (“RTL Synthesis”), Chapter 12 (“Logic Optimization”), Chapter 16 (“Technology Mapping”), Chapter 17 (“Timing-driven Optimization”), and Chapter 19 (“Powerdriven Optimization”). We will discuss verification aspects for a design in Chapter 9 (“Simulationbased Verification”), Chapter 11 (“Formal Verification”), Chapter 14 (“Static Timing Analysis”), and Chapter 18 (“Power Anlaysis”). We will present the information that is used both in implementation and verification in Chapter 13 (“Library”) and Chapter 15 (“Constraints”).

It is worthy to point out that the primary objective of these chapters is to build a foundation for logic design. Therefore, we explain essential concepts and principles governing it. We have attempted to provide explanations not based on any specific logic synthesis tool or proprietary data format. Therefore, a reader can apply these concepts to any tool s/he chooses for logic design. Additionally, note that these chapters build a foundation for logic design. To gain more depth on these topics, we encourage readers to refer to standard textbooks on them. We have provided references to those textbooks at appropriate places in each chapter.

In the previous chapters, we have discussed wafer-level testing that uses automatic test equipment (ATE). It allows a high degree of automation, achieves good fault coverage, and is cost-effective. Therefore, ATE-based testing is popular and widely adopted for industrial designs. However, ATEbased testing has the following drawbacks or limitations:

• 1. It requires expensive ATE. Moreover, it requires sophisticated facilities equipped with an ATE. We cannot perform it outside the production testing environment. However, sometimes testing, diagnosis, and repair become necessary for a chip that is already integrated into a system.

• 2. It employs voluminous test patterns that increase the test time and the cost of testing. Moreover, the number of test patterns increases with the advancement in technology due to increased circuit complexity. Consequently, the cost of testing increases with the advancement in technology.

• 3. We cannot carry out at-speed testing for high-performance integrated circuits (ICs) due to the impedances associated with the probes of an ATE [1]. However, some types of faults, such as delay faults, can only be detected by at-speed tests [2]. It makes ATE-based techniques inadequate in some situations.

Built-in self-test (BIST) is another testing methodology that addresses the above drawbacks and has become quite popular [3–6]. In this chapter, we will discuss BIST in detail.

We can implement BIST in a design in many ways, depending on the design complexity, target test metrics, and allowed overheads. In this chapter, we describe a typical BIST system to elucidate its basic principles.

BASICS

BIST is a testing technique in which we incorporate additional hardware and software in a chip that enables it to self-test. During self-testing, an IC can test its own operation, both functionally and parametrically. The self-testing does not require an external test pattern. Thus, we eliminate the dependence on an ATE. It allows us to carry out BIST-based testing in the field and even after system integration. Additionally, we can perform at-speed testing because no external signal interfacing is required.

In this part of the book, we will introduce integrated circuits (ICs) concepts and give a top-level view of the entire VLSI design flow. In the remaining portion of this book, we will discuss each task of the VLSI design flow in detail. We have taken this approach to present the topics because an early introduction to the entire design flow eases building context for individual tasks. It allows us to relate one task with another in the remaining portion of this book. We can appreciate the interaction between them and understand how decisions of one task impact other tasks. As a result, we can easily comprehend challenges and opportunities in optimizations and develop a solid understanding of the entire flow.

In the first chapter (“Foundation”), we will briefly describe the concepts of digital circuits, devices, CMOS inverters, data structures, and algorithms. Since readers would have been exposed to these topics previously, this chapter will serve as a refresher. Additionally, this chapter will be a handy reference if a reader needs to recall some of these concepts. In the second chapter (“Introduction to Integrated Circuits”), we will introduce the concepts related to ICs, their history, fabrication, economics, and figures of merit. In the third (“Pre-RTL Methodologies”) and fourth (“RTL to GDS Implementation Flow”) chapters, we will describe the implementation of a design from concept to the layout. In the fifth (“Verification Techniques”) and sixth (“Testing Techniques”) chapters, we will discuss basic concepts related to the verification and testing of ICs. In the seventh chapter (“Post-GDS processes”), we will explain processes involved in fabricating chips from a given layout.

In the previous chapters, we discussed the tasks required for designing an IC. Once we have obtained the final layout, the design process is complete. Subsequently, the GDS file corresponding to the final layout is employed for making a chip using tasks such as mask preparation, wafer fabrication, testing, and packaging. In this book, we have grouped all chip-making tasks carried out after obtaining the GDS file as post-GDS processes.

Though post-GDS processes are not directly related to the design flow, we need to understand them to appreciate the challenges of fabrication, and possibly address some of these challenges during the design phase. Therefore, we briefly explain post-GDS processes in this chapter. For a detailed understanding of post-GDS processes, readers can refer to dedicated books on these topics such as [1–5].

MASK FABRICATION

We have discussed in Chapter 2 (“Introduction to integrated circuits”) that an essential step in IC fabrication technology is photolithography. It involves transferring the patterns in a layout for a given layer to the silicon wafer. We carry out photolithography separately for each layer.

To start with, we create a replica of the pattern of a given layer on a substrate such as glass. This replica of the pattern is known as mask or reticle. After creating a mask, we use it many times for carrying out photolithography during high-volume manufacturing [4].

We can fabricate a mask using several techniques. Nevertheless, a typical mask fabrication flow consists of the following steps:

• 1. Data preparation

• 2. Mask writing and chemical processing

• 3. Quality checks and adding protections

We explain these steps briefly in the following paragraphs.

Data Preparation

First, we prepare the given layout data for mask writing. We translate the GDS-specified mask information to a format comprehended by a mask writing tool. It involves converting complicated polygons to simpler rectangles and trapeziums. This process is popularly known as fracturing. It simplifies the task for the mask writing hardware. Additionally, data preparation involves augmenting the mask data to enhance the resolution. We will describe some of these techniques later in this chapter.

In this chapter, we will discuss some of the basic concepts of design for testability (DFT). First, we will introduce the idea of structural testing and how it is different from functional testing. Then, we will explain fault model and its significance in testing. We will discuss single stuck-at fault model in detail. We will highlight the role of structural testing and the single stuck-at fault model in simplifying testing and making it cost-effective. We will also elucidate the problems of controlling and observing signals in a sequential circuit that are encountered during structural testing.

FUNCTIONAL TESTING VERSUS STRUCTURAL TESTING

Let us assume that we need to test a fabricated circuit that implements a Boolean function with N inputs. We can apply all possible 2N input combinations and check whether the outputs match the corresponding entries in the truth table. This is known as functional testing. However, when N is large (such as 50 or 100), the number of possible input combinations becomes dramatically large, and exhaustive functional testing of a circuit becomes infeasible. Therefore, we employ an alternative testing strategy known as structural testing for testing a fabricated circuit [1].

In structural testing, we test the components or hardware that implements a logic function rather than testing the input–output functionality of the implementation [1]. We can choose components at various abstraction levels such as transistors, switches, logic gates, standard cells, and macros (adders, multipliers, and arithmetic logical units (ALUs)). Nevertheless, we perform structural testing often at the level of logic gates. This testing is known as structural testing since it considers the topology and interconnections of logic gates in the implementation. The paradigm of structural testing is widely employed because it reduces the number of test patterns required for good test quality [2].

If we perform functional testing, we need to apply 216=65536 input combinations and compare the obtained circuit response with the correct response.

The previous chapter has dealt with digital circuits having output states dependent only on the instantaneous combination of the inputs. There exist yet another set of digital circuits, known as sequential logic circuits, which are presented in this chapter. A sequential digital circuit is almost always associated with a clock or a timer. This chapter illustrates the properties of a clock and explains several popular sequential digital circuits, namely flip-flop, register and counter that are the building blocks for many complicated digital systems including computer hardware.

Clock and Timer

First let us understand the meaning of the word ‘sequential’ sticking to some digital circuits. It is named so because:

Table 14.1 may be revisited in this occasion. Now the question arises, who makes this sequence to occur? That is the job of the clock and the timer. As explained in the previous chapters, digital circuits need two fixed and discrete voltage states as inputs. It is a very common phenomenon in a digital system, such as a computer that a number of circuits have to change the logic states in synchronism. That synchronizing is initiated by a timer and a clock.

The timer is an electronic circuit that generates a voltage waveform, generally square or rectangular, of well-defined amplitude and precise frequency. That voltage waveform of fixed amplitude and frequency generated by the timer is referred to as clock signal, clock pulse or simply clock. It defines a timing interval during which the circuit operations must be performed. Thus the timer is the ‘heart’ and the clock is the ‘heartbeat’ of a digital system. The clock has the following properties.

The absolute voltage values should comply with the circuit requirements.

In the previous chapter, we discussed design implementation: from RTL to the final layout. We carry out design implementation with the help of sophisticated EDA tools. These tools need manual inputs to gather design information, set tool options, and obtain hints to guide their algorithms. As a design gets transformed and moves through various EDA tools and design teams, bugs can creep into it. Some frequent bug sources are human error, miscommunication, inappropriate usage of EDA tools, and unexpected EDA tool behavior. These bugs can make a design erroneous. Therefore, it is critical to detect bugs or design problems using some verification techniques.

If design verification fails, we need to take some remedial actions. Therefore, it is prudent to verify a design as soon as we make some non-trivial design changes so that debugging and fixing effort is minimized. Hence, we need to verify a design multiple times during a design flow. Consequently, during designing, we spend significant effort on verification alone [1–3]. In the future, with the increase in design complexity, the verification effort is expected to increase further.

During various stages of a design flow, we employ different verification techniques. These techniques differ in exhaustiveness, computational resource requirement, and designer effort. In this chapter, we will briefly discuss some of the commonly used verification techniques. We will discuss these techniques in detail in Part II and Part IV of this book.

SIMULATION

During the early stages of a design flow, we represent the functionality of a design using an RTL model. Given a functionality, we can manually develop RTL models, reuse existing RTL, or generate them using a behavioral synthesis tool. Irrespective of the source, we need to verify that the RTL functionality matches the specification. Typically, we employ simulation to verify the functional correctness of an RTL model [4].

Using simulation, we mathematically compute the response of a given design for a given input or stimulus. We specify stimulus by a sequence of bits (0 or 1) at the input ports. We also specify the timing information such as when does 0 → 1 or 1 → 0 transition occur. A set of input stimuli applied to a circuit is commonly referred to as test vectors or test patterns.

This chapter introduces the types of semiconductors and their electrical properties. The origin of two types of charge carriers, namely electrons and holes in semiconductors are explained. The related theoretical concepts of energy band, Fermi energy and effective mass are introduced. The carrier transport in semiconductors causing drift and diffusion currents are discussed. Two important experimental techniques, namely Hall Effect and four-probe resistivity measurement are deliberated.

Crystalline Solids

A broad field of studies, known as condensed matter physics encompasses the macroscopic and microscopic physical properties of matter, mainly in the solid and liquid phases, being ‘condensed’ due to the electromagnetic forces between atoms. A part of this is solid state physics that studies the atomic level and bulk level properties of matter in its solid state. A solid is distinguished from liquid or gas by its definite shape and rigidity. This is because of the atoms or the molecules of a solid being closely packed and strongly bound. However, the atoms in a solid may or may not be in regular arrangement, which determines whether or not the solid is crystalline.

A semiconductor is generally a solid material having electrical conductivity level somewhere between that of conductors (e.g. metals) and insulators (e.g. ceramics). The conducting properties of semiconductors can be altered by application of external electrical fields, light and heat and by a process of incorporating impurities, known as doping. Devices made from semiconductors, such as diode, transistor and logic gates are the basic building blocks for modern electronic circuits. Before going through the properties of semiconductors, it is reasonable to get a brief idea on the fundamental properties of a crystalline solid.

A solid is called crystalline, if the atoms and the molecules in it are organized in symmetric arrays in three dimensions. A definite grouping of atoms is repeated periodically in three dimensions. If the crystal structure is perfect and the same regular arrangement is extended throughout the entire solid, it is called single crystal and if the periodicity is found to be intermittent and confined within a small region, it is called polycrystalline material. Solids not having such regular atomic arrangement are termed as amorphous.

As described in Chapter 4 (“RTL to GDS implementation flow”), we divide logic synthesis into two distinct phases: technology-independent phase and technology-dependent phase. The first task in technology-dependent phase is to map a netlist of generic gates to the cells of the given set of technology libraries. This task is known as technology mapping, or mapping in short. The tool or the software that carries out technology mapping is referred to as technology mapper, or mapper. Post-mapping we perform further technology-dependent logic optimizations [1, 2].

The attributes of timing, area, and power for cells are defined in a technology library. Therefore, mapping brings a significant transformation to a design by describing the timing, area, and power characteristics of each instance in a design. Consequently, the final quality of result (QoR) of a design depends heavily on the mapping. Moreover, post-mapping, the level of abstraction in a design decreases, and making further changes to the instances of a design becomes difficult. Thus, mapping is one of the most critical tasks of a design flow. We will discuss various aspects of mapping in this chapter.

BASICS OF MAPPING

The application framework of a technology mapper is shown in Figure 16.1. Let us examine its various components.

Inputs: A mapper takes a set of technology libraries, a given design, and constraints as inputs.

• 1. Technology libraries: A technology library consists of cells with different functions. For example, a library can contain cells implementing logic functions such as AND, OR, NOT, multiplexer, flip-flops, and latches. These cells can have a different number of inputs. For example, there can be cells implementing two-input AND gate, three-input AND gate, fourinput AND gate, etc. A mapper can use a combination of smaller gates or an equivalent big gate during mapping.

Before technology mapping, the netlist consists of generic gates. We refer to this netlist as unmapped netlist. After technology mapping, the netlist consists of cells from the technology libraries. We refer to this netlist as mapped netlist.

We have discussed logic optimization of unmapped netlist in Chapter 12 (“Logic optimization”). It primarily minimizes the circuit area. The delay estimates in an unmapped netlist are typically based on logic depth. These delay estimates can differ widely from the delay estimates of the mapped netlist. Therefore, we do not carry out timing-specific logic optimizations on an unmapped netlist.

We can perform static timing analysis (STA) on a mapped netlist using the associated technology libraries and the Synopsys Design Constraint (SDC) files. The timing models of library cells are trustworthy. Therefore, post-mapping STA fairly exposes potential timing issues in a design. Consequently, we can perform timing-driven optimizations on a mapped netlist. By timing-driven optimizations, we refer to design transformations that increase the maximum operable frequency of a circuit or fix timing issues in it.

In this chapter, we will discuss timing-driven optimizations that are performed on a mapped netlist.

MOTIVATION

To improve timing of a mapped netlist, one of the approaches can be to include the gate delays in the cost function within the mapping algorithm and allow the mapper to perform timing-driven optimizations [1–3]. However, this task is challenging, as explained below, and we can often find several opportunities for timing optimizations on the mapped netlist.

Challenges of timing-driven technology mapping: Technology mapping proceeds in two steps: finding matches for an unmapped gate (or vertex in an equivalent graph) and covering it.1 While finding suitable matches for an unmapped gate, we still have unmapped logic gates in its fanout. We do not know the input pin capacitance of the unmapped logic gates. Hence, it is challenging to compute delays of the possible matches because the gate delay depends on its output load. Therefore, we cannot select optimum cells that will be suitable for the future loading condition.

In the earlier chapters, we have discussed various tasks involved in a design flow. The design process culminates in sending the final layout to a foundry for fabrication or design tape-out. However, we do not start with the mass production of a chip immediately. Rather we check the first few samples of the fabricated chip by running actual applications under realistic operating conditions. This task is known as post-silicon validation. If we find problems in post-silicon validation, we need to debug and fix them before moving ahead with the mass production of a chip. In this chapter, we will discuss the basic concepts related to post-silicon validation.

NEED FOR POST-SILICON VALIDATION

During the pre-silicon phase, we perform verification on an abstract design model in a virtual environment using simulation, formal verification, and other techniques described in the earlier chapters. For complex designs and system-on-chips (SoCs), some verification gaps inevitably remain in the pre-silicon phase. Consequently, a fabricated chip can produce an unexpected or wrong response on an actual application. We need to detect such unexpected behavior of the fabricated chip and fix them before it reaches the end-users on a large scale.

Despite tremendous progress in the pre-silicon design verification techniques, we obtain errors in a majority of newly manufactured SoCs [1]. The primary reasons why verification gaps remain in the pre-silicon stage are as follows:

• 1. Inadequate functional coverage: The speed of simulation and other functional verification methods is orders of magnitude slower than obtaining results using a fabricated chip. The increasing complexity of integrated circuits (ICs), the exponential growth in the design space, and the tighter design schedule leave room for undetected functional issues in the pre-silicon stage. In contrast, we can verify the functionality of a fabricated chip by running software, operating systems (OS), and other real-world applications at full speed and for a longer duration, which is not possible using simulation-based verification. For example, we can execute the OS boot sequence on a fabricated chip in a few seconds, while simulating it using a register transfer level (RTL) model will require several years [2]. Hence, post-silicon validation allows us to cover those scenarios and operating conditions in the post-silicon validation stage that were missed during the pre-silicon functional verification.

In a sequential circuit, the controllability and observability of signals are low. The state elements (flip-flops) need to transition through several clock cycles before the value propagates from the input ports to an internal pin. We encounter a similar problem in observing the value of an internal pin at some output port. In the worst case, the number of clock cycles required to read or write a bit onto an internal pin can be exponential in the number of flip-flops. Even in a circuit with only a hundred flip-flops, the number of required clock cycles can make testing infeasible.

There are several problems associated with the low controllability and observability of signals. First, the tester will require a large number of clock cycles in applying the test pattern sequence. It increases the test execution time and the cost of testing. Second, it becomes difficult for the automatic test pattern generation (ATPG) tools to find the sequence of a test pattern for a given fault. The difficulty primarily arises because finding a test pattern in a sequential circuit requires state exploration or searching for the appropriate sequence of states. Since, in general, there can be too many states, finding a test pattern sequence in a sequential circuit becomes challenging. Therefore, the test development time becomes dramatically high for a sequential circuit. Consequently, we might need to sacrifice the fault coverage, and the quality of testing can suffer.

We can tackle the above problems by employing the scan design methodology. In this methodology, we modify the sequential circuit to improve signal controllability and observability. Consequently, test pattern generation and test pattern application by the tester become extremely efficient. In this chapter, we will explain the scan design methodology in detail.

BASICS OF SCAN DESIGN TESTING

The basic principle of a scan design methodology is to make design modifications such that controlling and observing the state of memory elements in a design becomes easier than in the original sequential circuit [1].

Salient features: The salient features of scan design methodology are listed below and illustrated in Figure 21.1.

Designing an electronic system is a complicated process. We simplify the design process by decomposing it into multiple tasks. As we carry out these tasks, an abstract “idea” of a system gradually transforms into a design and finally into the desired product. During this transformation, creating a register transfer level (RTL) model is a milestone. However, before RTL model creation, several tasks need to be carried out. In this book, we refer to these tasks collectively as pre-RTL methodologies.

Pre-RTL methodologies involve determining various components and their interactions that achieve the desired functionality at a high level of abstraction. These components can be hardware or software. The hardware components can be processors, memories, peripherals, sensors, data converters, and signal processing blocks. The software can be firmware, device drivers, operating systems, and application programs. Since pre-RTL methodologies involve taking decisions at the system level, we also refer to the pre-RTL design activities collectively as system-level design.

At the system level, we have only a few necessary constraints of the system. Therefore, we have a greater freedom in choosing components, and many feasible solutions are possible. However, evaluating the impact of different choices is challenging because we have limited implementation details. Nevertheless, choices made during system-level design strongly impact the quality of the final product. Therefore, system-level design is critical, as well as challenging.

We have been doing IC-related system-level design for the last several decades. However, due to diverse application-specific issues, system-level design methodologies could not be standardized [1]. Till date, system-level design consists of widely varying tools and technologies [2–8]. For example, system-level design methodologies can differ between a signal processing chip (such as a video encoder and decoder) and a multicore processor. Therefore, in this chapter, we describe a few methodologies that are applicable in diverse scenarios. Subsequently, readers can apply the concepts explained in this chapter to different applications and platforms. To know more about system-level design, we suggest that readers refer to dedicated books on system-level design such as [1, 9–12].