This chapter presents optical receivers that intentionally limit the bandwidth so as to achieve higher gain and better sensitivity. This has the consequence of introducing that ISI that must be removed by a suitable equalizer. Important aspects of the noise analysis of these receivers are clarified. Various approaches to equalization in these reduced bandwidth receivers are presented by way of recently published examples.

Beginning with a discussion of receiver metrics, this chapter discusses electrical-link receiver implementation by first considering input termination and ESD capacitance mitigation. The receiver front-end has two main jobs. The first is to amplify the signal to levels that can be captured by a decision circuit and the second is to remove enough ISI such that low BER detection is possible. With the types of receive-side equalization already described at the system level in Chapter 4, this chapter focuses on their transistor-level implementation. Both CML and inverter-based circuits are presented.

This chapter presents advanced topics that draw on the fundamentals of previous chapters. Section 11.1 presents how implementing PAM4 signalling impacts equalization and circuit design. A brief overview of DAC/ADC-based links, also known as DSP-based links, is presented in Section 11.2. A consequence of PAM4 signalling is a smaller vertical eye opening. A digital equalization technique known as “maximum likelihood sequence estimation” is discussed in Section 11.4.

This chapter, along with the next three, covers the general topic of clock generation and distribution as well as clock and data synchronization. Clocking circuitry, including clock and data recovery systems can dissipate 30–50% of total transceiver power. Jitter degrades BER as much as amplitude noise. Therefore wireline designers must pay attention to the jitter performance of clock generation circuitry and clock distribution circuitry as much as they focus on the amplitude noise behaviour of the receiver’s signal path. Although clock generation can dissipate non-trivial power, the centralized generation of a clean reference clock allows the amortization of its power dissipation across multiple transceiver lanes, although its distribution is also challenging. Therefore, a thorough treatment of all aspects of clocking is important. This chapter gives an overview of the principal synchronization approaches used in wireline systems as well as clock distribution circuitry.

In this chapter we introduce circuits that are used to generate clocks. After an introduction to the metrics of oscillators, this chapter introduces the main categories of oscillators, and how they are made voltage-controlled. The important trade-offs between power, phase-noise, and tuning range are explained. Methods for converting a VCO to a digitally controlled oscillator are included in Section 14.4.

Electrical-link design is challenging due to the frequency-dependent loss and reflections associated with electrical channels as well as cross-talk between nearby channels. The equations describing lossless and lossy transmission lines are introduced in this chapter, followed by a brief discussion of loss mechanisms. The characteristics of various channels are presented, along with the effect of wirebonds and packages. The goal of this chapter is to provide link designers with a methodology to estimate the overall pulse response of a channel consisting of a lossy transmission line and the relevant package and chip parasitic elements. Knowing the pulse response, a link designer can then contemplate and model the equalization (discussed in Chapter 4) needed to properly detect transmitted bits. This chapter is organized to discuss transmission-line fundamentals and then overall channels.

Mixed-signal wireline receivers use sensitive, high-speed decision circuits to compare input signals to a well-defined threshold, allowing the decoding of received bits. This chapter gives the important metrics of these circuits and contrasts their operation against that of conventional D flip-flops. Two main classes of circuit are discussed, namely current-mode logic and sense-amplifier-based circuits. The basics of their operation are presented. Simulation strategies and offset compensation are discussed.

This chapter starts with an overview of the requirements of an electrical-link transmitter. Electrostatic discharge protection is required in CMOS processes. The large capacitance it adds severely loads the output driver. The main mitigation strategies are presented here, focusing on T-coil-based compensation, a type of inductive peaking. In Section 1.12, two categories of circuits were introduced, namely CML and CMOS. These give rise to current-mode and voltage-mode transmitters, both of which are presented in this chapter. Impedance control and the implementation of feed-forward equalizers is discussed. A reader who is primarily interested in optical transceiver design should read this chapter before moving on to Chapter 8.

A central challenge in the design of electrical links is to compensate for frequency-dependent loss in the channel that introduces inter-symbol interference (ISI). This chapter presents the overall objectives of joint Tx/Rx equalization. The system-level operation of transmitter-side feed-forward equalizers (FFEs) is discussed. Circuit details are presented in Chapter 5. Receiver-side continuous-time linear equalizers (CTLEs) and finite-impulse-response (FIR) filters are discussed next, followed by decision-feedback equalizers (DFEs). DFEs differ from FFEs, CTLEs and FIRs in that they only remove ISI rather than attempt to invert the low-pass channel characteristic. With the growing trend toward ADC- based receivers, the implementation of DFEs and Rx FFEs is discussed in the analog domain and the digital domain. The topics in this chapter are also a relevant background for the sections in Chapter 10 that discuss TIAs for reduced bandwidth systems, where equalization is used to remove ISI from an intentionally bandwidth-limited optical receiver front-end.

This chapter builds on the basic transmitter building blocks presented in Chapter 5 and applies them to optical links. The section on direct modulation discusses CML and SST circuits for driving laser diodes, along with how equalization can be added, incorporating concepts from Chapter 4. One aspect of laser diodes that is presented is their nonlinear behaviour that favours having different equalization for rising and falling edges, something not typically done in electrical links where channels are linear. Circuit design for modulator drivers is discussed in Section 8.2, including an overview of distributed amplifiers. Finally, microring modulator drivers are presented in Section 8.3. Since the basic IC building blocks have already been introduced in Chapter 5, this chapter emphasizes aspects particular to driving optical devices, such as the electrical modelling of the electronics/photonic packaging and the challenges in producing voltage swings beyond the breakdown voltage of the underlying CMOS technology.

This chapter introduces wireline communication, focusing on introducing key terminology, such as eye diagrams, intersymbol interference, noise, bit-error ratio, pulse response, non-return-to-zero modulation, pulse-amplitude modulation. The similarities and differences between electrical and optical links are discussed. Exemplary transceiver block diagrams are presented.

This chapter begins with a recapitulation of an optical link and what the general requirements of an optical receiver are. The discussion of optical receivers starts with a brief analysis of a passive current-voltage converter (i.e., a resistor) in terms of its gain, bandwidth and input-referred noise. This section proposes reasonable bandwidth requirements for optical receivers that do not use equalizers, so-called low-ISI systems. Open-loop and feedback amplifiers are considered. Additional amplification through main-amplifier design is explained, starting with the effect on bandwidth of cascading multiple first-order stages. Behaviour of second- and third-order systems are also presented. Examples of Cherry-Hooper, second-order active feedback and third-order active feedback as well as interleaving feedback are presented. CMOS inverter-based designs are discussed.

Every designer of integrated circuits for optical transceivers needs to be familiar with the fundamentals of optical channels and the devices that convert electrical signals to optical signals and vice versa. This chapter provides a concise overview starting with optical fibre. Single-mode and multi-mode fibre are described as well as the characteristics of on-chip optical channels. Optical-to-electrical conversion through photodiodes is discussed along with simple electrical models. Considerations for implementing photodiodes entirely in silicon are included in a separate section. On the transmitter side, both direct modulation and indirect modulation are presented. This chapter summarizes the physics of laser diodes and gives a simplified model of the electrical dynamics and their electrical to optical conversion. Similarly, an electrical model and a model for E/O conversion will be presented for Mach–Zehnder interferometer-based modulators. The chapter closes with an overview of silicon photonics.

With PLLs and ILOs introduced in Chapter 14, this chapter introduces and presents the systems that synchronize clocks to incoming data, known as clock and data recovery (CDR) systems. The chapter starts with an introduction and discussion of the metrics of CDRs. Phase detection is done differently in CDRs compared to PLLs. This is explained before the most common approaches are described. Several options are available to the designer for how phase comparisons should be acted on. These are presented and compared next. The chapter continues with an introduction to baud-rate phase detection schemes built on Mueller–Muller phase detection.

This chapter presents systems that use a voltage-controlled oscillator in a feedback loop to lock its phase to that of a reference clock. These systems, called phase-locked loops (PLLs), generate the signals used to clock decision circuits and MUX/DEMUX circuits. An introduction to PLLs and the notion of phase comparison starts this chapter. The typical Type II analog PLL is analyzed. Split tuning and details of frequency division are presented. Digital PLLs are now commonplace necessitating an overview. Injection-locked oscillators (ILOs) play an important role as clock buffers and multiphase generators This chapter gives an overview of ILO dynamics covering topics of jitter-tracking bandwidth, lock range and injection strength.