In the previous chapter we saw that positive feedback can be useful – though it is the underdog in feedback circuitry, less important than the great strategy of negative feedback. It can make a switching circuit decisive, and it allows construction of oscillators.

In this chapter we will begin with an introduction to interrupts, then learn how to configure I/O pins for input, first to read a pushbutton and then to scan a matrix keyboard. We will also look at creating Finite State Machines in the microcontroller.

We are going to configure the SERCOM with the simplest of the three protocols, SPI, requiring only a clock and data line along with an optional device select line.

This chapter presents optical receivers that intentionally limit the bandwidth so as to achieve higher gain and better sensitivity. This has the consequence of introducing that ISI that must be removed by a suitable equalizer. Important aspects of the noise analysis of these receivers are clarified. Various approaches to equalization in these reduced bandwidth receivers are presented by way of recently published examples.

Beginning with a discussion of receiver metrics, this chapter discusses electrical-link receiver implementation by first considering input termination and ESD capacitance mitigation. The receiver front-end has two main jobs. The first is to amplify the signal to levels that can be captured by a decision circuit and the second is to remove enough ISI such that low BER detection is possible. With the types of receive-side equalization already described at the system level in Chapter 4, this chapter focuses on their transistor-level implementation. Both CML and inverter-based circuits are presented.

This chapter presents advanced topics that draw on the fundamentals of previous chapters. Section 11.1 presents how implementing PAM4 signalling impacts equalization and circuit design. A brief overview of DAC/ADC-based links, also known as DSP-based links, is presented in Section 11.2. A consequence of PAM4 signalling is a smaller vertical eye opening. A digital equalization technique known as “maximum likelihood sequence estimation” is discussed in Section 11.4.

This chapter, along with the next three, covers the general topic of clock generation and distribution as well as clock and data synchronization. Clocking circuitry, including clock and data recovery systems can dissipate 30–50% of total transceiver power. Jitter degrades BER as much as amplitude noise. Therefore wireline designers must pay attention to the jitter performance of clock generation circuitry and clock distribution circuitry as much as they focus on the amplitude noise behaviour of the receiver’s signal path. Although clock generation can dissipate non-trivial power, the centralized generation of a clean reference clock allows the amortization of its power dissipation across multiple transceiver lanes, although its distribution is also challenging. Therefore, a thorough treatment of all aspects of clocking is important. This chapter gives an overview of the principal synchronization approaches used in wireline systems as well as clock distribution circuitry.

In this chapter we introduce circuits that are used to generate clocks. After an introduction to the metrics of oscillators, this chapter introduces the main categories of oscillators, and how they are made voltage-controlled. The important trade-offs between power, phase-noise, and tuning range are explained. Methods for converting a VCO to a digitally controlled oscillator are included in Section 14.4.

Electrical-link design is challenging due to the frequency-dependent loss and reflections associated with electrical channels as well as cross-talk between nearby channels. The equations describing lossless and lossy transmission lines are introduced in this chapter, followed by a brief discussion of loss mechanisms. The characteristics of various channels are presented, along with the effect of wirebonds and packages. The goal of this chapter is to provide link designers with a methodology to estimate the overall pulse response of a channel consisting of a lossy transmission line and the relevant package and chip parasitic elements. Knowing the pulse response, a link designer can then contemplate and model the equalization (discussed in Chapter 4) needed to properly detect transmitted bits. This chapter is organized to discuss transmission-line fundamentals and then overall channels.

Mixed-signal wireline receivers use sensitive, high-speed decision circuits to compare input signals to a well-defined threshold, allowing the decoding of received bits. This chapter gives the important metrics of these circuits and contrasts their operation against that of conventional D flip-flops. Two main classes of circuit are discussed, namely current-mode logic and sense-amplifier-based circuits. The basics of their operation are presented. Simulation strategies and offset compensation are discussed.

This chapter starts with an overview of the requirements of an electrical-link transmitter. Electrostatic discharge protection is required in CMOS processes. The large capacitance it adds severely loads the output driver. The main mitigation strategies are presented here, focusing on T-coil-based compensation, a type of inductive peaking. In Section 1.12, two categories of circuits were introduced, namely CML and CMOS. These give rise to current-mode and voltage-mode transmitters, both of which are presented in this chapter. Impedance control and the implementation of feed-forward equalizers is discussed. A reader who is primarily interested in optical transceiver design should read this chapter before moving on to Chapter 8.