Defines the level (high or low) in which a signal is “True,” or – better – “Asserted” (see next term). We avoid the former because many people associate “True” with “High,” and that is an association we must break.

Here we will do a problem much like the one we did more sketchily in . If you are comfortable with the design process, skip to §§3W.1.6 and 3W.1.7, where we meet some new issues.

In the lab exercises, from now and ever after, you will want to be able to read resistor values without pulling out a meter to measure the part’s value (we do sometimes find desperate students resorting to such desperate means). The process will seem laborious, at first; but soon, as you get used to at least the common resistance values, you will be able to read many color codes at a glance.

Here’s a statement of the design task, and some questions:

We want to solve the problem of optimizing circuit performance by selecting from the great variety of available op-amps. We will try to make sense of the fact – not predictable from our first view of op-amps as essentially ideal – that there are not one or two op-amps available but approximately 30,000 listed (on the day of this writing) on one distributor’s website (DigiKey).

The problem – just analysis this time: This is a rare departure from our practice of asking you to design, not to analyze. Inventing a difference amp1 seemed a tall order, and, on the other hand, the difference amplifier’s behavior seems far from obvious. So, here’s a little workout in seeing how the circuit operates.

Serial data input and output are classic applications where interrupt-driven I/O makes sense. Rather than sit in a loop wasting CPU cycles waiting for each byte to be sent or received, an ISR can load a new byte into the output register each time the previous byte has been sent, or store each new byte in a buffer as they are received.

Please check the errata page at https://LAoE.link/Installing_the_FPGA.html before you begin to see if there have been any updates or changes to the procedure below.

Insert the shorter pins of the 2x5 SWD header from the top of the board and solder from the rear. Use care to avoid solder bridges on the closely spaced pins of this connector: see Fig. 22S.2.

Why? Finite State Machine design methodology provides a rigorous way to design synchronous systems. It applies not only to hardware but to software design as well (as we shall see when we study embedded microcontrollers).

Now that we have seen that sequential circuits are almost always (the SR and transparent latches being the exceptions) designed with edge-triggered logic, we need to look at what can go wrong with edge triggering if we are not careful.

Here are reminders of Nyquist’s sampling rule and some consequences, with scope images of artifacts that sampling can introduce.

Figure 13L.1 gives a preview of what’s coming in the form of waveforms at several points. Before you have built the circuits, these waveforms may be a bit cryptic; but trying to understand these plots may help you to get a grip on the whole project. Then we’ll finish these lab notes with some suggestions on how to test your circuits.

You will need to download, install, and modify the Segger embOS according to the following instructions before beginning Lab 27L.

In this chapter we meet an amplifier sensitive to a difference between two inputs rather than to a difference from ground. This novelty permits implementation of the hugely important operational amplifier, which from the next class onward will be our principal analog building block.

You now have a working DAC available in your microcontroller. We are going to use the built-in ADC to allow us to digitize analog signals as well. Once you’ve got these peripherals available, it’s fun to try altering waveforms, fun to see the result on a scope and fun to hear the result.

Setting particular thresholds exactly can be a pain in the neck. The process may put you through tedious algebra. But there are two easy cases.