Are we pushing the breathless pace of this course too far in proposing to dispose of Field Effect Transistors (FETs) in a day? We gave more time to bipolar transistors, and much more to operational amplifiers.

Today you will first build and test a simple RAM in the FPGA. You will then build a seven-segment decoder ROM and connect it to the output of the FPGA 74HC161 counter you designed in the last lab to show the count on an LED display.

You saw a DIP1 in the previous lab. Fig. 6L.1 shows another, this time an 8-pin mini-DIP, housing the operational amplifiers that we will meet in this and later labs.

Here is a method for spot-checking a suspected bad transistor: the transistor must look like a pair of diodes when you test each junction separately. But, caution: do not take this as a description of the transistor’s mechanism when it is operating: it does not behave like two back-to-back diodes when operating (the circuits of Fig. 4L.1, if made with a pair of ordinary diodes, would be a flop, indeed).

Most students learn pretty quickly to read resistor values. They tend to have more trouble finding, say, a 100 pF capacitor.

Part of what we aim for today is a review, since the circuit includes an unusually broad variety of elements. What you will achieve is the wireless transmission of an audio signal, using optical encoding.

This lab presents two devices, both partially digital, that have in common the use of feedback to generate an output related in a useful way to an input signal. The first circuit, an analog-to-digital converter, uses feedback to generate the digital equivalent to an analog input voltage.

Available at https://LAoE.link/LAoE_Chapter_17O.pdf.

So what really happens when a program loads? When an interrupt event occurs? Well, a lot!

In addition, packaged logic gates are low density, typically containing only a few gates.1 That means any reasonably complex digital systems might need tens or hundreds of DIP packages. Because signals have to travel between packages, systems built with discrete logic are limited in speed as well.

AoE works a similar problem in detail: §2.2.5A. The example below differs in describing a follower for AC signals. That makes a difference, as you will see, but the problems are otherwise very similar.

In the last chapter’s Worked Examples, we looked at several digital comparators constructed out of gates. We certainly could translate those to structural models in Verilog, but that misses the point. The advantage of an HDL is it frees us from truth tables, Boolean equations, and the need to implement the result with logic gates. Instead, we can describe the desired result behaviorally.

Use a logic probe, not DVM or – worse – your eyes This should go without saying, but we’re not sure it yet does. We find it boring to stare at a wire, trying to see if it goes where it should.