9.1 INTRODUCTION

In the preceding chapter, we intensively discussed the concept of negative feedback and its effects on amplifiers in detail. In the present chapter, the effect of feedback will be discussed in the context of working and analysis of oscillator circuits to generate sinusoidal and non-sinusoidal pulses and waveforms. The basic concept of oscillator differs from that of an amplifier. An amplifier amplifies a given AC input signal by using the DC power supply VCC and resistive networks to provide proper bias and stability with the aid of negative/degenerative feedback so as to stabilize gain and enhance bandwidth of operation. As completely opposed to this, an oscillator circuit needs no input AC signal. The power supply DC input VCC helps in picking up noise signals from its wide frequency spectrum, which due to regenerative/positive feedback networks and amplifier, gets sustained in the oscillatory circuit. Hence DC input gets converted into AC output. Thus, an oscillator can also be referred to as AC-DC converter. The working of an oscillator is exactly opposite to rectifier; hence it can be called an ‘inverter’. But it should be well understood that an oscillator does not create energy, instead it converts unidirectional current drawn from DC source into alternating current of desired frequency. Hence, the oscillator can be broadly defined as an amplifier with positive feedback. The difference between amplifier and oscillator is explained in the block diagram of Figure 9.1(a).

9.2 CLASSIFICATION OF OSCILLATORS

Oscillators can be broadly classified using following two aspects,

• a) Classification based on design principle

• b) Classification based on frequency of oscillation

a) Figure 9.2 shows the detailed family tree of various types of oscillators based on the design principle.

From Figure 9.2, based on the design principle, commonly used oscillators can be broadly classified as harmonic and relaxation oscillators. Harmonic oscillators generate sinusoidal waveforms, whereas relaxation oscillators generate pulse/rectangular/sawtooth waveforms. The basic tuning circuit for harmonic oscillators can be made of combination of L-C networks, which are suitable for generating RF (radio frequency) oscillations from 720 KHz up to hundreds of MHz, whereas R-C networks are suitable for generating AF (Audio Frequency) oscillations in the range of 20 Hz–20 KHz. The detailed description of each of the oscillator is performed in subsection 9.5 and 9.6.

Almost every undergraduate engineering discipline starting from electronics, electrical, computer science, instrumentation engineering, information technology, mechanical engineering, biotechnology etc. requires a solid foundation in basic electronics which comprises a study of fundamental devices like diodes, transistors and their applications in designing amplifiers, switching/logic circuits etc. While for some disciplines, a basic understanding might be sufficient, for other disciplines like electronics, electrical etc., this course acts as an important building block in the curriculum. Moreover, for various advanced courses like analog electronics, digital circuits and VLSI, in-depth understanding of basic electronics is a prerequisite. This book is written keeping both these aspects in mind and as a result it will serve undergraduate students of various engineering disciplines. In addition, it can also cater to the needs of college and university students belonging to disciplines like physics, electronics, and also in electronics courses in polytechnics. A competent electronics engineer, even in the modern era of integrated-circuit based design, needs a thorough and solid understanding of the basic concepts of semiconductors and a firm grasp of fundamental devices like diodes and various kind of transistors. This book attempts a perfect balance between housing all the basic concepts in accordance with the syllabi of leading institutes and universities and a thorough understanding required for future courses. In solid state electronics and analog electronics, which normally appears at a later stage of the undergraduate electronics curriculum, the approach is significantly different: while solid state electronics provides more emphasis on device physics and detailed understanding, analog electronics concentrates more on the applications, where the device is generally treated as a black box. Even though these two advanced courses are mutually dependent on each other, there exists a significant gap between the two approaches and undergraduate students face real difficulties in making a correlation and correspondence between them. This book attempts to minimize this gap between the different approaches to solid state devices and analog circuits. Special care has been taken to explain all the semiconductor devices in this book from both, physical and circuit approaches. To facilitate this, extra stress is given in chapters 2 and 3 while discussing crystal structures and the p-n junctions.

11.1 INTRODUCTION TO THYRISTOR

Thyristors are able to switch large levels of power and are used in a wide variety of different applications. Thyristors find use in low-power electronics, where they are used in many circuits ranging from light dimmers to power supply over voltage protection. The idea of thyristor was first described by William Shockley in 1950. It was referred to as a bipolar transistor with a p-n hook collector. The mechanism for the operation was analysed further in 1952 by Jewell James Ebers and in 1956 John L. Moll investigated the switching mechanism of the thyristor.

The first silicon-controlled rectifiers became available in the early 1960s when it started to gain a significant level of popularity for power switching. It is a multilayered semiconductor device which requires a gate signal to turn it ‘ON’. Once it is turned ‘ON’, it behaves like a rectifying diode. Thus, the name silicon-controlled rectifier is justified by its working principle. In fact, the circuit symbol for the thyristor suggests that this device acts like a controlled rectifying diode.

Four layers are formed by alternating n-type and p-type semiconductor materials. Consequently, there are three p-n junctions formed in the device. It is a bistable device. The three terminals of this device are anode (A), cathode (K) and gate (G). The gate (G) terminal is the control terminal of the device. The circuit symbol is shown in the Figure 11.1.The current flowing through the device is controlled by electrical signal applied to the gate (G) terminal. The anode (A) and cathode (K) are the power terminals of the device which can handle large applied voltage and conduct the major current through thyristor. For example, when the device is connected in series with load circuit, the load current will flow through the device from anode (A) to cathode (K) but this load current will be controlled by the gate (G) signal applied to the device externally.

11.2 CONSTRUCTION: REALIZATION USING TRANSISTORS

Unlike the normal p-n junction diode, which is a two-layer semiconductor device, or the transistor, a three layer (p-n-p or n-p-n) device, the Thyristor is a four-layer (p-n-p-n) semiconductor device that contains three p-n junctions in series, as shown in Figure 11.2.

This book provides a rigorous yet intuitive explanation of jitter and phase noise as they appear in electrical circuits and systems. The book is intended for graduate students and practicing engineers who wish to deepen their understanding of jitter and phase noise, and their properties, and wish to learn methods of simulating, monitoring, and mitigating jitter. It assumes basic knowledge of probability, random variables, and random processes, as taught typically at the third- or fourth-year undergraduate level, or at the graduate level, in electrical and computer engineering.

The book is organized as follows: Chapter 1 provides a qualitative overview of the book and its contents. Chapter 2 covers the basics of jitter, including formal definitions of various types of jitter and the key statistical concepts, starting from jitter mean and the standard deviation up to random and deterministic jitter. Phase noise will be first introduced in Chapter 3, and its relation to jitter and to the voltage spectrum of the clock signal will be extensively investigated. In particular, how to derive from phase noise the values of the several jitter types introduced previously will be explained. Chapter 4 is dedicated to the effects of jitter and phase noise in basic circuits and in basic building blocks such as oscillators, frequency dividers, and multipliers. Chapters 5 to 8 discuss the effects of jitter and phase noise in various circuit applications. Chapter 5 is dedicated to the effects of jitter on digital circuits, Chapter 6 to data converters, Chapter 7 to wireline, and Chapter 8 to wireless systems. More advanced topics on jitter are covered in Chapter 9, followed by numerical methods for jitter in Chapter 10. This chapter also explains how to generate jitter and phase noise, with various characteristics, for simulation purposes. The corresponding Matlab code for producing jitter is included in Appendix B.

As mentioned earlier, this book assumes the reader has a basic knowledge of random variables and random processes. However, to refresh the reader's memory of the definitions of some key terms, Appendix A simply lists these key terms along with their basic definitions.

Guidance for the Reader

The book does not require the reader to adhere strictly to the order in which the chapters appear, nor to read all of them.

The most common approach to the investigation of the behavior of electronic systems in the presence of jitter is to use linear modeling in the frequency domain and phase noise profiles. However, especially in the presence of complex or non-linear systems, it is often beneficial to perform transient simulations and evaluate the results in the time domain. To use this approach, it is necessary to provide numerical methods to, first, generate clock signals in the time domain that have given phase noise profiles and, second, analyze the results of transient simulations and possibly convert them into phase noise plots. The goal of this chapter is to provide some of these techniques.

Most of the chapter is dedicated to algorithms and numerical recipes to generate jitter samples with several different phase noise profiles, and to compute jitter and phase noise given a vector of time instants, typically obtained from transient simulations. Following that, basic algorithms to perform tail fitting are presented. All algorithms are implemented and demonstrated using Matlab and are coded such that they can be easily ported to any other common programming language. The code is included in Appendix B.

Numeric Generation of Jitter with Given Phase Noise Profiles

The problem addressed in this section is how to generate a sequence of numbers tk representing the instants of the edge transitions of a clock having nominal frequency f0 and a desired phase noise profile L(f).

As a starting point, the sequence tk can be decomposed into the sum tk = tid,k + ak of a vector describing an ideal clock, tid,k = k/f0 with k ≥ 0, and a vector ak describing the jitter process. Note that the ak corresponds to the absolute jitter, according to the definition given in Section 2.1.1. The problem translates then into the generation of the sequence ak showing a given phase noise profile L(f).

Before proceeding it is important to recall that the PSD of the sequence ak is independent from its probability density function (PDF). To make it clearer, imagine one realization of the process ak being plotted on a graph, where the x-axis is the index k and the y-axis is the value (amplitude) of ak.

This chapter recalls the definitions and the insights introduced in Chapter 2 and elaborates on them in mathematical terms. It gives the reader a more complete understanding of the subject from a mathematical point of view, and provide tools and techniques to analyze quantitatively jitter issues in real systems. The mathematical foundations are reviewed in Appendix A.

In the main part of the chapter, the relation between phase noise and jitter is treated in depth. Examples of phase noise profiles are taken from those most common in practice, and their corresponding jitter is derived. The effect of spectral spurious tone on jitter is also considered and analyzed.

Basic Relationship Between Jitter and Excess Phase

In the following sections, the jitter concepts presented in the previous chapter will be related to the excess phase. Unless otherwise noted, we will assume a clock signal as described by Equation 2.2, and we refer the reader to Section 2.1 for a more generic discussion of the concept of an ideal clock and excess phase.

Excess Phase and Absolute Jitter in the Time Domain

The theory of phase noise is based on the assumption that the excess phase due to noise in electronic systems is a continuous-time process. This assumption is very well justified in practice. Indeed, even though the ultimate sources of noise – the charge carriers in the devices – are intrinsically quantized, noise events normally involve such a large number of particles and occur at such a high frequency that, for all practical purposes, even on a very small time scale, their effects can be considered continuous.

Jitter, on the other hand, can be defined and measured only when a clock transition is occurring, so it is intrinsically a discrete-time process. In this section we clarify the dependencies of the two processes.

If we assume a generic clock, represented by x(ω0t) periodic in T0 = 2π/ω0, where the term ω0t is the total phase of the signal, the time instants of the clock transitions can be defined as the time when the signal crosses a given constant threshold value with, e.g., positive slope. By properly choosing the origin of the time axis, the k-th clock transition occurs when the total phase is equal to 2πk.

In this chapter we analyze the effect of jitter on synchronous digital systems. We will first introduce the register (also known as flip-flop) as the central element of the design, its associated timing requirements, and the standard configuration for edge-triggered digital design. After analyzing the effect of jitter on the standard configuration, the reader will be introduced to the case of divided clock systems, enabled systems and multicycle systems. Finally, a section is dedicated to latch-based digital design and the effect of jitter on it.

Edge-Triggered Synchronous Design

In modern integrated systems, the vast majority of the digital functions are implemented in edge-triggered synchronous design. The central element of these systems is the register, a circuit which transfers to its output the digital value of its input, on the occurrence of the edge of a clock signal. Shown in Figure 5.1 is the symbol of a register and the corresponding timing waveforms. In an ideal register, when the rising edge of the clock signal CK occurs, the output Y assumes immediately the value of the input X at that particular instant. In practice, a register behavior differs from the ideal in at least three aspects. First, in order to be able to capture the input data correctly, the input data has to be stable some time before the rising edge of CK. This time is called setup time and is indicated by τsu. Second, the input data is not allowed to change its value for some time after the rising edge of CK. This time is called the hold time and is indicated by τho. Third, even if setup and hold time constraints are satisfied, there is a propagation delay from input to output, so that the new data appears at the output Y some time after the rising edge of CK. This time is typically called the clock-to-Q, and is indicated by τcq.

Figure 5.2 illustrates the typical configuration encountered in synchronous edgetriggered designs. A first register, or bank of registers, samples the incoming data X1 with the clock CK and produces the output Y1. This output is processed by a combinatorial logic network, and its result X2 is fed to the input of a second register, or bank of registers. The second register samples the processed data X2 with the same clock CK, and produces the output Y2.

A wireline communication system sends and receives data based on precise timing. Any deviation from the ideal timing, i.e., jitter, has a direct impact on the bit error rate (BER) at the receiver. Figure 7.1 shows a generic block diagram of a wireline transceiver that consists of a transmitter, a channel, and a receiver. The role of the transmitter is to serialize N binary sequences, generated by the core logic, into one binary sequence DTX, and send it reliably over the channel to the receiver. If we assume, for example, that the core logic produces 16 data sequences (i.e., N = 16), each at 500Mb/s, then the transmitter will produce a single binary sequence at 8Gb/s. The channel could be a few meters of cable (e.g., between a computer and a peripheral), a few inches of PCB trace (e.g., between a microprocessor and a memory module on the same board), or a few millimeters of an interconnect in a multi-chip module. In all these cases, the channel tends to attenuate the high-frequency components of the signal, and degrade the received eye both in the voltage domain (vertical axis) and in the time domain (horizontal axis). The received signal timing is further degraded due to the jitter in the transmitter clock (CKTX), which in turn may be caused by thermal noise in the clock generation circuit or by power supply noise. In the presence of all these jitter components, the receiver must be designed so as to recover the transmit bits reliably, e.g., at a BER better than 10-12 or 10-15. In this chapter, we first review various sources of the jitter that limits the BER, and then provide techniques for jitter characterization, jitter monitoring, and jitter mitigation.

As mentioned in Chapter 1, jitter does not always work against performance; there are cases where we can use jitter to improve system performance. We provide two such examples later in this chapter.

Basic Concepts in Wireline Signaling

A wireline transmitter, in its simplest form, sends a non-return-to-zero (NRZ) binary signal to the receiver. The wireline receiver first equalizes the received signal so as to compensate for the channel loss (or equivalently to remove the channel ISI) and then samples the equalized signal, using a recovered clock at the center of the data eye to see whether the sampled value is above or below a threshold.

In the industry as well as in academia, the concept of jitter is sometimes treated using approximations, leading to misunderstandings and possibly to systems which are not optimally designed with respect to jitter performance. This chapter lays the foundation for a thorough and clear understanding of jitter in practice.

The chapter starts by providing four fundamental definitions of jitter: absolute jitter, relative jitter, period jitter and N-period jitter. It proceeds with an overview of other jitter definitions commonly found in literature. It will be shown that these additional definitions can be expressed in terms of the four fundamental jitter definitions.

A large part of the chapter handles the important topic of jitter statistics and the estimation of key parameters such as root mean square (RMS) and peak or peak-peak values. This will lead to the classification of jitter based on its distribution, and eventually to the introduction and explanation of the concepts of deterministic jitter, random jitter and total jitter.

General Jitter Terminology and Definitions

A variety of terms are commonly used to express the concept of jitter, and several different definitions can be found in the open literature, mostly dependent on the particular background of the author or on the specific application considered. A short and incomplete list of these terms includes period jitter, cycle jitter, cycle-to-cycle jitter, N-period jitter, accumulated jitter, adjacent jitter and long-term jitter. It is not uncommon to find the same term used with different meanings by different authors, leading to possible misunderstandings and confusion.

In this chapter jitter will be defined according to the way it can be measured, at least in principle. This will not result in jitter definitions that are different from the ones already found in the literature; rather, it will put the existing definitions in a clear and solid framework. These operative definitions of jitter turn out to be very intuitive, simple and of high practical value. Since the definition is connected to a measurement process, it is easier to relate it to a specific application. And, conversely, given a specific application, this approach makes it is easier to find the relevant jitter definition.

Generally speaking, jitter is the deviation of the time instant at which a given event occurs, relative to a reference time frame, which can be chosen arbitrarily.

A wireless transceiver typically uses a PLL at the transmitter to up-convert a baseband signal to an RF frequency and uses another PLL at the receiver to down-convert the RF signal back to the baseband. Depending on the quality of the PLL clock, which is often measured by its phase noise, the process of up-conversion and down-conversion produces unwanted signals which often interfere with signals in adjacent channels and deteriorate the SNR at the receiver. In this chapter, we first provide a brief background on the transmitter and receiver concepts, and then discuss the impact of PLL phase noise on transceiver performance.

Basics of Wireless Transceivers

Figure 8.1(a) shows the block diagram of a simplified wireless transmitter, in which a baseband signal is up-converted to an RF frequency in a two-step process: first to an intermediate frequency (IF), and then to an RF frequency, using a local oscillator (inside a PLL). The RF signal is then fed to a bandpass filter (BPF) followed by a power amplifier (PA) and the antenna. If the oscillator produces a pure single tone, the up-converted signal will simply contain the baseband signal translated (shifted) in frequency to fRF. If the baseband signal has a bandwidth of B, the RF signal will have a bandwidth of 2B, as shown in Figure 8.1(b). However, due to the phase noise of the oscillator, the up-converted signal will also contain frequency content outside the 2B bandwidth, which may contribute to noise in adjacent receiver channels. The BPF allows the signal and the noise content within the 2B bandwidth to pass but attenuates the phase noise and other noise content that lie outside the 2B bandwidth. The PA amplifies the power of the RF signal so as to extend its reach to the intended receivers.

A simplified block diagram of a wireless receiver is shown in Figure 8.2(a). The received signal from the antenna is first filtered by an off-chip surface acoustic wave (SAW) filter, then passed to a low noise amplifier (LNA), and subsequently to a mixer that down-converts the RF signal either to an intermediate frequency (IF) or directly to DC for further filtering.

This chapter will offer an introduction to how jitter and phase noise are generated in the most common oscillator topologies. Starting with the treatment of basic circuits like a current charging a capacitor, or an inverter, we will continue by analyzing jitter and phase noise generation in ring, relaxation, and LC oscillators. Both linear time invariant and linear time variant approaches will be illustrated.

The chapter will finish with an overview of how jitter is “transformed” by two of the most common frequency processing circuits: a digital frequency divider and an ideal frequency multiplier.

Jitter in Basic Circuits

The next sections provide an explanation, both qualitative and quantitative, of how jitter manifests itself in basic oscillator circuits.

Noisy Current Charging a Capacitor

As mentioned already in Section 1.3, in integrated circuit design a central element is a current loading a capacitor. Digital gates, clock buffers, delay elements of relaxation and ring oscillators are just few examples of where this element can be found. Due to its ubiquity and importance, it is worth analyzing in some detail from the standpoint of jitter generation. In the following we will revisit the example provided in Section 1.3, and treat it with a complete mathematical analysis. The case of a PMOS transistor charging a capacitor is shown in Figure 4.1. The case of an NMOS discharging the capacitor is identical.

The goal of this analysis is to derive an expression for the variation of the time instant at which the charging voltage crosses a given threshold V0 (see Figure 4.1). The first step is to recognize that the resulting time deviation is due to two different components. The first is the effect of the noise current in injected into the capacitor by the PMOS during the charging transient. The second is due to the fact that, even if the capacitor is considered discharged at time zero, there is voltage noise present on it due to the circuitry which is used to keep it discharged. This noise can be considered as a random initial vertical offset which will affect the threshold crossing time.