Design data sanity

• Are design data fully consistent? Have all design modifications always been propagated? Has the design data base never been tampered with (e.g. using a text or stream editor)?

• Are you sure that no source data such as HDL specifications, schematics, netlists, macrocell generator instructions, and the like have been modified after physical design was begun?

• Have all verification steps (simulation, ERC, timing verification, DRC, LVS, etc.) been carried out on the most recent version of the design?

• Do the cell libraries and/or transistor models being used indeed apply to the fabrication process and the operating conditions targetted?

• Have all library elements been fully characterized? Beware of “0” or other default entries sometimes entered by library developers for properties (such as area, propagation delay, power dissipation, etc.) the numerical values of which have not yet been established.

Pre-synthesis design verification

• Is a bit-true and cycle-true behavioral model available (in HDL, C, or Matlab)? Has this circuit model been thoroughly tested in system-level simulations? Have the system designers checked and accepted the results so obtained?

• Do the logic gauges used in simulating a behavioral model systematically cover all modes and conditions under which the circuit is going to operate?

• Do the logic gauges also address uncommon situations, such as exceptional control flows, corrupt input data, numeric exceptions (e.g. divide by zero), overflows and underflows, truncation and rounding, data values outside of their habitual range, non-rational frequency ratios, and the like?

Agenda

Physical design is concerned with turning circuit netlists into layout drawings that

• Are amenable to fabrication with some given target process,

• Logically function as expected in spite of numerous parasitic effects,

• Meet ambitious performance goals in spite of layout parasitics, and

• Keep fabrication costs down by minimizing die size and by maximizing yield.

The degree to which physical issues are placed under control of IC designers is highly dependent upon fabrication depth and design level. While global interconnect must be planned for in every design project — even when opting for field-programmable logic — few digital designers continue to work with layout at the detail level today. This chapter is organized accordingly. Sections 11.2 through 11.4 cover issues that are relevant in any IC design, such as floorplanning and packaging, while the material on detailed layout is postponed to section 11.5. Section 11.6, finally, collects discussions of various destructive phenomena that must be contained.

Conducting layers and their characteristics

The layers made available by VLSI processes greatly differ in their geometric and electrical characteristics. Let us begin by studying those properties and differences.

Geometric properties and layout rules

The transfer of layout patterns to the various layers of material on a semiconductor die is obtained from photolithographic methods followed by selective removal of unwanted material.

Motivation

Why hardware synthesis?

VLSI designers constantly find themselves in a difficult situation. On the one hand, buyers ask for microelectronic products that integrate more and more functions on a single chip. Following Moore's law, fabrication technology has always supported this aspiration by quadrupling the achievable circuit complexity every three years or so. Market pressure, on the other hand, vetoes a proportional dilation of product development times. Worse than this, time to market is even supposed to shrink. As a consequence, design productivity must constantly improve.

Hardware description languages (HDLs) and design automation come to the rescue in three ways: they

• Exonerate designers from having to deal with low-level details by moving design entry to more abstract levels,

• Allow designers to focus more strongly on functionality as synthesis tools construct the necessary circuits along with their structural and physical views automatically, and

• Facilitate design reuse by capturing a circuit description in a parametrized technology- and platform-independent form (as opposed to schematic diagrams, for instance).

Today, the transition from structural to physical is largely automated in digital VLSI design. The transition from purely behavioral to structural has not yet reached the same maturity, but HDL synthesis is routinely used for turning register transfer level (RTL) descriptions into gate-level networks that are then processed further with the aid of cell-based design automation software. A digital HDL essentially must be able to describe how subcircuits interconnect to form larger circuits and how those individual subcircuits behave functionally and timingwise.

Interconnect model reduction has emerged as one crucial operation for circuit analysis in the last decade as a result of the phenomenon of interconnect dominance of advanced VLSI technologies. Because interconnect contributes to a significant portion of the system performance, we have to take into account the coupling effects between subcircuit modules. However, the extraction of the coupling renders many small fragments of parasitics. While the values of the parasitics are small, the number of fragments is huge and this makes the accumulated effect non-negligible. If left untreated, the amount of parasitics can gobble up the memory capacity and consume long CPU time during circuit analysis.

Model reduction transforms a system into a circuit of much smaller size to approximate the behavior of the original description. Many researchers have contributed to the advancement of the techniques and demonstrated drastic reduction of the circuit sizes with satisfactory output responses in published reports. Many of these techniques have also been implemented in software tools for applications. However, it is important for the users to understand the techniques in order to use the package properly. To adopt these approaches, we need to inspect the following features.

1. Efficiency of the reduction: the complexity of the reduction algorithm determines the CPU time of the model reduction. The size of the reduced circuit affects the simulation time.

2. […]

In this chapter, we exploit a new way of passive modeling interconnect circuits by so-called signal waveform shaping. Traditional passive modeling methods try to ensure that the reduced models are strictly passive using passive-preserving model order reduction methods or passivity enforcement optimization methods, as shown in Chapter 2 and Chapter 10. In this chapter, we show that passivity can also be achieved by slightly altering (shaping) the waveforms passing through the reduced models.

Introduction

Many model order reduction (MOR) techniques have been proposed in the past. The most efficient and successful one is based on subspace projection [32, 37, 85, 91, 113], which was pioneered by asymptotic waveform evaluation (AWE) algorithm [91] where explicit moment matching was used to compute dominant poles at low frequencies. After AWE, more numerical stable techniques were proposed [32, 37, 85, 113] by using implicit moment matching and congruence transform to produce passive models. A detailed review of Krylov subspace methods can be found in Chapter 2.

Another important development in linear MOR is the introduction of truncated balanced realization (TBR) methods, where the weak uncontrollable and unobservable state variables are truncated to achieve the reduced models [81, 87, 89, 131]. The TBR methods can produce nearly optimal models but they are more computationally expensive than projection-based methods.

Compact modeling of passive RLC interconnect networks has been an intensive research area in the past decade owing to increasing signal integrity effects and interconnect-dominant delay in current system-on-a-chip (SoC) design [72].

In this chapter, we briefly review the existing modeling order reduction (MOR) algorithms for linear time-invariance (LTI) systems developed over the past two decades in the electrical computer-aided design community. Since compact modeling of TLI systems is a well researched and studied field, many efficient approaches have been proposed over the years. Given the space in this book, we cannot review all of them and neither do we attempt to be complete in our review. Instead, we mainly review the Krylov subspace projection-based model order reduction methods, which are widely used MOR methods and are closely related to the rest of this book. Although there exists an excellent and detailed treatment of Krylov subspace projection-based methods already [14], for the completeness of this book, we still present some basic concepts, algorithms and important results for Krylov subspace projection-based MOR methods. We try to present them in a way that can be easily understood from the practical application point of view.

Moments and moment-matching methods

In this section, we briefly review the concepts of time-domain moments, the Elmore delay and Pade-approximation-based moment-matching method, which are important concepts for subspace projection-based model order reduction methods.

In this chapter, we present some general compact model optimization and passivity enforcement algorithms. Model optimization can be viewed as a fitting-based model generation process, where we fit a parameterized model against the simulated or measured data of original circuits. Model optimization methods can be applied to more general modeling applications like modeling RF and microwave circuits where it is difficult to obtain the models directly from the structures of the circuits. Instead, engineers typically model those circuits by fitting full-wave simulation or measured data. One critical issue in such applications is the preservation of some important circuit properties like passivity and reciprocity.

In this chapter, we introduce some efficient model optimization and passivity enforcement methods, as well as some reciprocity-preserving modeling methods developed in recent years.

Passivity enforcement

In this section, we present the state-space based passivity enforcement method, which is based on the method used in [21], but we will show how this method can be used in the hierarchical model order reduction framework to enforce passivity of the model order reduced admittance matrix Ỹ(s).

Passivity is an important property of many physical systems. Brune [12] has proved that the admittance and impedance matrices of an electrical circuit consisting of an interconnection of a finite number of positive R, positive C, positive L, and transformers are passive if and only if its rational function are positive real (PR).

Introduction

In the chapter, we introduce another structure-preserving model order reduction method, which extends the SPRIM method [37] to more general block forms while the 2q moment-matching property is still preserved. The SPRIM method partitions the state matrix in the MNA (modified nodal analysis) form into natural 2 × 2 block matrices, i.e., conductance, capacitance, inductance, and adjacent matrices. Accordingly, the projection matrix is partitioned. As a result, SPRIM matches twice the moments of the models by using the projection matrix given by PRIMA. The reduced models also preserve the structural properties of the original models like symmetry (reciprocity). This idea has been extended to deal with more partitions by block structure-preserving model order reduction (BSMOR) [136], as shown in Chapter 8 to further exploit the regularity of the many parasitic networks. It was shown that by introducing more partitions, more poles are matched and this leads to more accurate order-reduced models [138].

However, the BSMOR method simply introduce more partitions or blocks; it does not truly preserve the circuit structures for general RLCK circuits for different input sources (voltages or currents). The reduced model does not match the 2q moments of the original models, as SPRIM does.

In this chapter, we first show theoretically that structure-preserving model order reduction can be applied to RLCK admittance networks, which are driven by voltage sources and requires partitioning of the original MNA circuit matrix into 2 × 2 block matrices.

In this chapter, we focus on passive wideband modeling of RLCM circuits. We propose a new passive wideband reduction and realization framework for general passive high-order RLCM circuits. Our method starts with large RLCM circuits, which are extracted by existing geometry extraction tools like FastCap [83] and FastHenry [59] under some relaxation conditions of the full-wave Maxwell equations (like electro-quasi-static for FastCap or magneto-quasi-static for FastHenry) instead of measured or simulated data. It is our ultimate goal that we can obtain the compact models directly from complex interconnect geometry without measurement or full-wave simulations. The method presented in this chapter is called hierarchical model order reduction, HMOR, which is based on the general frequency-domain hierarchical model reduction algorithm [121, 122, 124] and an improved VPEC (vector potential equivalent circuit) [134] model for self and mutual inductance, which can be easily sparsified and is hierarchical-reduction friendly.

The HMOR method achieves passive wideband modeling of RLC circuits via multi-point expension and the convex programming based passivity enforcement method. In this section, we will show that the frequency-domain hierarchical reduction is equivalent to implicit moment-matching around s = 0, and that the existing hierarchical reduction method by one-point expansion [121, 124] is numerically stable for general tree-structured circuits.

Introduction

Model order reduction methods for linear and non-linear dynamic systems in general can be classified into two categories [6]:

1. Singular-value-decomposition (SVD) based approaches

2. Krylov-subspace-based approaches.

Krylov-subspace-based methods have been reviewed in Chapter 2. In this chapter, we focus on the SVD-based reduction methods. Singular value decomposition is based on the lower rank approximation, which is optimal in the 2-norm sense. The quantities for deciding how a given system can be approximated by a lower-rank system are called singular values, which are the square roots of the eigenvalues of the product of the system matrix and its adjoint. The major advantage of SVD-based approaches over Krylov subspace methods lies in their ability to ensure the errors satisfying an a-priori upper bound. Also, SVD-based methods typically lead to optimal or near optimal reduction results as the errors are controlled in a global way. However, SVD-based methods suffer the scalability issue as SVD is a computational intensive process and cannot deal with very large dynamic systems in general. In contrast, Krylov-subspace-based methods can scale to reduce vary large systems due to efficient computation methods for moment vectors and their orthogonal forms.

SVD-based approaches consist of several reduction methods [6]. In this chapter, we mainly focus on the truncated-balanced-realization (TBR) approach and its variants, which were first introduced by Moore [81].