Delay fault testing exposes temporal defects in an integrated circuit. Even when a circuit performs its logic operations correctly, it may be too slow to propagate signals through certain paths or gates. In such cases, incorrect logic values may get latched at the circuit outputs.

In this chapter, we first describe the basic concepts in delay fault testing, such as clocking schemes, testability classification, and delay fault coverage.

Next, we present test generation and fault simulation methods for path, gate and segment delay faults in combinational as well as sequential circuits. We also cover test compaction and fault diagnosis methods for combinational circuits. Under sequential test generation, we look at non-scan designs. Scan designs are addressed in Chapter 11.

We then discuss some pitfalls that have been pointed out in delay fault testing, and some initial attempts to correct these problems.

Finally, we discuss some unconventional delay fault testing methods, which include waveform analysis and digital oscillation testing.

Introduction

Delay fault (DF) testing determines the operational correctness of a circuit at its specified speed. Even if the steady-state behavior of a circuit is correct, it may not be reached in the allotted time. DF testing exposes such circuit malfunctions. In Chapter 2 (Section 2.2.6), we presented various DF models, testing for which can ensure that a circuit is free of DFs. These fault models include the gate delay fault (GDF) model and the path delay fault (PDF) model.