From the previous chapter we learned that the mobile charge carriers in a semiconductor can be categorized as electrons in the conduction band and holes in the valence band. The carriers occupy states, which define their energy and crystal momentum. One of the objectives of this chapter is to determine the density of these states in energy or momentum, as well as the densities of the carriers in real space. We begin, however, with a look at how the mobile carriers are created and destroyed.

Creation of electrons and holes

The four mechanisms by which electrons (in the conduction band) and holes can be created in the devices discussed in this book can be classed as thermal, optical, electrical, and chemical.

Thermal generation

For temperatures T > 0 K, the lattice atoms vibrate about their mean positions. Occasionally, the local amplitudes of vibration are sufficient to break a valence bond, i.e., to release an electron from the valence band. Obviously, in a perfectly periodic crystal, the energy gained by the electron must be sufficient to promote the electron into the conduction band, as there are no available states elsewhere. The situation is illustrated in Fig. 3.1, where an electron from state 〈1〉 in the valence band is promoted to state 〈1′〉 by the absorption of phonons.

The first part of this chapter is dedicated to the MOS sample-and-hold circuit (S/H). The main physical limitations of the MOS S/H, namely switch on-resistance, thermal noise, and switch charge injection, are reviewed. Distortion produced by the non-linear switch resistance is modeled and some circuit-linearization techniques for MOS switches are introduced as well as low-voltage circuit techniques. Finally, clock-jitter effects on the MOS S/H are modeled and these effects in analog-to-digital converters are commented on. The second part of the chapter presents the basics of switched-capacitor (SC) circuits. Parasitic insensitive integrators and second-order filters are reviewed. Amplifier specifications for SC circuits are detailed, as well as some circuit techniques to reduce the effects of op-amp imperfections. The important topic of SC circuits fully compatible with digital MOS technology ends the section on SC circuits. The last part of the chapter briefly introduces alternative switched circuits, specifically switched-MOSFET and switched-current filters.

MOS sample-and-hold circuits

Sample-and-hold (or track-and-hold) circuits are ubiquitous in signal-processing circuits. They are used at the front end of analog-to-digital (A/D) converters and at the back end of digital-to-analog (D/A) converters. The signal-to-noise ratio of an A/D converter is usually limited by the performance of the sample-and-hold block. Furthermore, precision analog integrated circuits are mostly implemented by sampled-data circuits in which the basic building block is the S/H.

Sample-and-hold basics

An ideal S/H is depicted in Figure 10.1. During the sampling mode, the switch S is on and the output voltage tracks the input voltage.

Predicting the future is the realm of prophets and gamblers. Generally speaking, engineers belong to neither of these groups. However, it is evident that the trend in high-performance transistors is towards smaller and smaller devices, so we might reasonably expect this to continue into the near future. This miniaturizing trend has led, in the early part of the 21st century, to much talk about nanoelectronics. In my opinion, nanoelectronics does not mean, contrary to popular belief, merely the scaling down of transistors to devices with feature sizes of the order of tens of nanometres. If it did, then present-day devices, such as InGaP/GaAs HBTs with basewidths of around 30 nm, Si MOSFETs with channel lengths of ≈40 nm, and InAlAs/InP HJFETs with channel thicknesses of a few nanometres, would already qualify as nanotransistors.

What nanoelectronics implies, to me at least, is the fabrication of transistors from the ‘bottom up’, rather than from the ‘top down’. The latter process is the one that applies to all the HBTs, MOSFETs, and HJFETs discussed in earlier chapters: it involves the making of something small from something large using photolithographic masking techniques. Contrarily, a true nanotransistor is built-up from something even smaller, such as a molecule or a nanoparticle. This opens up opportunities for new methods of self-assembly (perhaps using biological recognition), and for new 3-D circuitry (perhaps using a molecular backbone), that cannot be matched using conventional processing techniques.

When neighbouring regions of a homogeneous semiconductor are doped with different types of dopant, a pn- or np-junction is formed. When the junction is between different semiconductors, the junction is labelled either Pn or Np, where the capital letter denotes the doping type of the semiconductor with the higher bandgap. Semiconductor/semiconductor junctions play a crucial role in solar cells, LEDs, bipolar transistors, and HJFETs, and are prominent also in MOSFETs. As we demonstrate in this chapter, a potential energy barrier forms at this type of junction. In a solar cell, this barrier facilitates the separation of photogenerated electron-hole pairs into a current. In the other devices, the modulation of the junction barrier height by an applied voltage allows the current to be controlled by external circuitry.

In this chapter the focus is mainly on the np-junction; it is used to achieve an understanding of the properties of semiconductor junctions via the drawing of an energy-band diagram, the construction of which is explained here. We also introduce the concepts of quasi-neutrality and quasi-Fermi levels. The latter prove useful in describing carrier concentrations under non-equilibrium conditions. Finally, the Np-junction is described, and some consequences of the bandgap mismatch are noted.

np-junction at equilibrium

To construct the equilibrium energy-band diagram for an np-junction, consider first Fig. 6.1a, in which the separate n- and p- type regions are shown.

This chapter begins by explaining briefly why there is still a need for analog design and introduces its main tradeoffs. The need for accurate component modeling follows. Then, the essentials of p–n junctions and bipolar and field-effect transistors (FETs) for circuit design are recalled. The main differences between bipolar-transistor and FET operations are emphasized and drawbacks of some popular FET models for circuit design are commented on. Finally, two single-stage amplifiers, one in bipolar and another in MOS technology, are designed in order to make the differences between these technologies clear.

Analog design

The need for analog design

Analog circuits such as audio and radio amplifiers have been in use since the early days of electronics. Analog systems carry the signals in the form of physical variables such as voltages, currents, or charges, which are continuous functions of time. The manipulation of these variables must often be carried out with high accuracy.

On the other hand, in digital systems the link of the variables with the physical world is indirect, since each signal is represented by a sequence of numbers. Clearly, the types of electrical performance that must be achieved by analog and digital electronic circuits are quite different, and for this reason they are generally studied in separate university courses.

Nowadays, analog circuits continue to be used for direct signal processing in some very-high-frequency or specialized applications, but their main use is in interfacing computers to the analog world.

Power amplifiers and switch-mode power supplies are two instances where the constituent transistors are required to deliver higher currents, and to withstand higher voltages, than are encountered in the digital, high-frequency and memory transistors discussed previously. In this chapter we briefly describe the structural details of, and discuss the principal properties of, several types of high-power transistor: the GaAs HBT and GaN HJFET for power amplification, and the Si MOSFET and hybrid transistor for power supplies.

High currents mean high carrier densities, which can lead to a modification of the space-charge region at the output junction (collector/base or drain/body), with consequences for the frequency response and/or the breakdown voltage. We begin this chapter with a description of the breakdown process (avalanche breakdown), and of the high-current, space-charge-modifying effect (the Kirk Effect).

Avalanche breakdown

Operating transistors at high VCE or high VDS can lead to electrical breakdown of the collector/base or drain/body junction, respectively. Breakdown is characterized by the sudden onset of a large current which, if it is not interrupted, can lead to thermal destruction of the transistor. The breakdown process in a reverse-biased pn-junction is illustrated in Fig. 16.1.

Electrons entering the high field of the junction rapidly gain kinetic energy. If this energy is allowed to exceed the bandgap energy Eg, then, when the electron finally collides with a lattice atom, an energy E ≥ Eg can be transferred to another electron, thereby exciting it into the conduction band.

Compact models, which describe the electrical behavior of the passive and active devices on a chip, are the fundamental link between circuit designers and foundries. Compact models allow simulation of the circuit functionality before its fabrication, thus saving time and money. In CMOS technologies, the MOS transistor is the principal component; consequently, its model plays a decisive role in the analysis and design of integrated circuits.

Early compact MOSFET models rely on approximate solutions that are valid only in particular regions of operation, which are connected mathematically by smoothing functions. Because the threshold of strong inversion VT is the key parameter in these regional models, they are also called VT-based models. This regional approach leads to inaccuracy between regions and, consequently, this class of models is not accurate enough to represent the moderate-inversion region. To overcome the limitations of VT-based MOSFET models, a new class of models emerged, namely inversion-charge-based and surface-potential-based models.

This chapter provides an overview of the approaches taken by the developers of MOSFET models. After a brief review of VT-based MOSFET models, we present a summary of some fundamental properties of advanced MOSFET models.

The accuracy of the transistor characteristics depends not only on an appropriate device model but also on the accuracy of its fundamental parameters. To complete the chapter we describe some procedures to extract fundamental parameters of MOSFET models, in particular those used in this textbook as design parameters.

Semiconductor memory is one of the main drivers of the semiconductor industry. Competition is fierce to increase density, and to reduce power dissipation and access times. In this chapter we describe two very important and much-used types of memory cell, each based on the Si MOSFET: flash memory, and dynamic random access memory (DRAM). Both memories, and, indeed, all semiconductor memories, have the basic organizational structure shown in Fig. 15.1a. The feature of flash memory and DRAM that gives them their capability of exceptionally high density is the use of a single transistor for the memory element (see Fig. 15.1b).

Flash memory is used in computer BIOS, and has also enabled many popular products, e.g., memory sticks, digital cameras, and personal digital assistants. There is some interesting physics in this non-volatile memory element: data is stored as charge on a floating gate within the insulator of a MOSFET. Charging and discharging is achieved ‘in a flash’ via field-assisted tunnelling.

DRAM is the main memory in PCs and workstations. Data is stored in a capacitor attached to the source of a pass transistor. As we show later, the action of reading a ZERO changes the stored data, so the memory has to be refreshed periodically, hence the appellation ‘dynamic’. Leakage of charge from the storage capacitor also dictates that there be frequent refreshing of the memory's contents.

Analog designers require MOSFET models that are accurate for (numerical) circuit simulation, but they also need models that are simple enough to allow design (at a symbolic level) that captures the essential non-linearity of the transistors. Clearly, the analysis and design models must be consistent in order to allow a smooth transition between design and analysis. Ever since the origins of MOS circuit design, until recently, the most popular compact models for design have been based on the threshold-voltage (VT) formulation. This class of models relies on approximate solutions that are accurate only in the limit cases of strong- and weak-inversion operation, and no accurate model is available for the transition (moderate-inversion) region between them. VT models are no longer acceptable for analog circuits in advanced, low-voltage technologies, where the moderate-inversion region is increasingly important. For this reason, compact models strongly based on the MOS transistor theory, which are accurate in all the operating regions of the transistor, will be summarized in this chapter. The fully consistent and simple charge-based MOSFET model will be reviewed in Section 2.1. The model presented here preserves the symmetry of the conventional rectangular-geometry transistor, an important property on which several circuits are based. A design-oriented current-based model is summarized in Section 2.2. The dynamic models, including expressions for nine linearly independent capacitive coefficients of the four-terminal transistor and a non-quasi-static model are presented in Section 2.3, and the main short-channel effects are rapidly reviewed in Section 2.4.

Originally, the most significant difference between a MOSFET and a BJT was the high input impedance afforded by the gate insulation of the FET. The high quality of the SiO2/Si system in Si MOSFETs has not proved possible to replicate in other semiconductor systems, particularly those involving III-V compound semiconductors. Therefore, to capitalize on the advantages that the latter semiconductors may have over silicon, such as mobility (see Fig. 11.1), and still realize a FET device, some other way of implementing the field-effect is necessary. This has been done by using a metal/semiconductor junction, rather than a metal/insulator/semiconductor combination, to create a vertical field to control the charge in the channel. The two main devices that exploit this are shown in Fig. 11.2: the MESFET (metal-semiconductor FET), and the HEMT (high-electron-mobility transistor). The latter device is also sometimes called a MODFET, where MOD refers to modulation doping, and relates to the fact that the doping in the top barrier layer plays a key role in controlling (modulating) the channel charge. All these transistors are HJFETs (heterojunction FETs) on account of the presence of a metal/semiconductor heterojunction in their structures.

The use of high-mobility semiconductors in MESFETs and HEMTs enables attainment of a high transconductance, which is a prerequisite for good high-frequency perfomance (see Section 14.4).

This chapter begins with a rapid overview of CMOS technology for circuit designers, including the description of a simplified deep-submicron CMOS structure and its process flow as well as the main parameters of some representative processes. The devices available in CMOS processes, including resistors, capacitors, inductors, and bipolar transistors, are then reviewed. The main electrical parameters of the passive devices are presented. Some design issues related to the use of sub-wavelength optical lithography are addressed in the introduction to the layout sections. Finally, layout topics, including design rules and layout for manufacturability, for matching, and for transistor associations, are presented.

An overview of CMOS technology

MOS integrated circuits (ICs) have been manufactured for volume delivery ever since 1970. Taking advantage of the scalability of the MOS transistors, micron technologies were developed during the 1980s and deep-submicron technologies appeared in the 1990s. In this chapter we will briefly review some deep-submicron processes that are currently (2009) employed for analog design.

Basic process steps in monolithic IC fabrication

Monolithic ICs are fabricated on high-quality monocrystalline silicon substrates called wafers, with diameters as large as 300 mm and thicknesses up to 1250 μm. The fabrication process enables the achievement of appropriate geometries in the semiconductor and in the insulating and conducting layers deposited on the semiconductor substrate. The fabrication process consists of a series of elementary steps that allows the patterning of the semiconductor substrate and the modification of its electrical properties by selective doping as well as the deposition, removal, and patterning of conducting and insulating layers.

The large-signal models of Fig. 13.16 and Fig. 13.19 are to be used when considering DC and switching operations. High-frequency operation is governed by the small-signal performance of transistors. It is insightful, and computationally efficient, to develop a small-signal model of the transistor by linearizing the large-signal model. Our approach is to linearize via a Taylor series expansion, and then manipulate the resulting equivalent circuit so that it can be used to define and evaluate two important high-frequency metrics: fT and fmax.

Small-signal operation is illustrated in Fig. 14.1, which shows a simple amplifier. The base-emitter DC bias is supplied from the power-supply VBB via a resistor, and the small AC signal is supplied from vin via a capacitor. The transistor is of the bipolar variety, in recognition of the fact that bipolar transistors (BTs) have traditionally been dominant in high-frequency applications. This dominance has been due principally to the BT's transconductance being inherently superior to that of FETs, as we will show later in the chapter.

Presently, the world record for fT is 710 GHz, and is held by an HBT based on the sleek-looking device shown in Fig. 14.2. However, nowadays, FETs are encroaching into the high-frequency domain: HEMTs using high-mobility semiconductors based on GaAs and InP can yield devices with very high transconductance; and MOSFETs employing silicon's matchless technology can yield very small devices, for which the capacitance is very low.

Analog filters, essential parts in many different electronic systems, can be implemented in CMOS using switched-capacitor (SC), switched-current (SI), active-RC, MOSFET-C, or OTA-C techniques. Owing to their considerable importance in analog CMOS circuits, Chapter 10 will focus on SC circuits. In this chapter, we study the MOSFET-C and OTA-C techniques, which have been the most important ones for the realization of continuous-time (CT) integrated filters in CMOS technologies. Applications of CT filters include anti-aliasing and reconstruction filters, read channels of disk drives, data-communication circuits, and high-speed data links. A disadvantage of CT filters is that the filter coefficients are sensitive to process and temperature variations and aging. Therefore, tuning of the components that determine the frequency response is required. In this chapter, we will concentrate on the fundamental aspects of filter design at the component level and on the basic building blocks for each technique. We will describe some of the main limitations of the MOSFET-C and OTA-C techniques and the concepts of some tuning schemes used for keeping the filter transfer function close to the nominal specifications. The synthesis of high-order filters, which can be found in more specialized texts such as, is not the subject of this chapter.

Basics of MOSFET-C filters

The MOSFET-C (MOSFET-capacitor) is a mature technique for the integration of CT filters in CMOS technologies. MOSFET-C circuits are similar to the active-RC topologies composed of operational amplifiers, resistors, and capacitors.

The MOSFET was the subject of a patent in 1933, but did not reach commercial maturity until about thirty years later. The delay was principally due to a lack of understanding of the importance of the oxide/semiconductor interface, and to the time taken to develop suitable fabrication procedures, notably for the growth of the thin gate oxide. Now, in the early 21st century, the science of silicon, and the art and technology of its processing into electronic devices have reached such a state of maturity that billions of Si MOSFETs are made weekly. The claim that the Si MOSFET is the most abundant object made by mankind is difficult to refute.

In this chapter the so-called ‘long-channel’ FET is considered. The basic electrostatics of the device is developed, and the DC current-voltage characteristics are derived using two models that are very widely used in the simulation of Si MOSFET integrated circuits: PSP and SPICE. PSP stands for ‘Penn-State Philips’, after the two organizations that have been largely instrumental in bringing this surface-potential model to a state of commercial viability. It is the Compact Model Council's new, industrialstandard, MOSFET model. SPICE stands for ‘Simulation Program with Integrated Circuit Emphasis’. It was originally developed by Lawrence Nagel at the University of California at Berkeley in the mid-1970s, and has evolved extensively since then. PSP is surface-potential based, whereas SPICE is threshold-voltage based.

The picture of charge carriers that should have emerged so far is one of electrons and holes moving through the semiconductor in momentum states. The carriers are continually being generated and annihilated, and they are also frequently scattered to new momentum states via collisions with vibrating atoms, ionized impurities and other carriers. In thermal equilibrium large fluxes are present, but there is no net current. To disturb this equilibrium, and obtain a non-zero net flow of charge, we need to establish some driving force within the semiconductor. Fundamentally, this driving force is a gradient in energy. It can be manifest as a gradient in the potential energy, which is related to the electrostatic potential ψ, and as a gradient in kinetic energy. If each of the n electrons per m3 has a kinetic energy u, the total kinetic energy density W is nu. Gradients in both n and u can produce a current. The main objective of this chapter is to describe and characterize the currents due to each of these three gradients.

The above picture is one of dissipative transport, i.e., one in which the directed momentum of electrons injected into a region from a hemi-Maxwellian distribution, for example, is dissipated by scattering events. If the region is so short that the injected electrons can traverse it without being scattered, then we have ballistic transport.