Soldering to Cu interconnect pads with Sn-containing alloys usually leads to the formation of a layered Cu3Sn/Cu6Sn5 structure on the pad/solder interface. Frequently, microscopic voids within Cu3Sn have been observed to develop during extended thermal aging. This phenomenon, commonly referred to as Kirkendall voiding, has been the subject of a number of studies and speculations but so far the root cause has remained unidentified. In the present work, 103 different Cu samples, consisting of 101 commercially electroplated Cu and two high-purity wrought Cu samples, were surveyed for voiding propensity. A high temperature anneal of the Cu samples before soldering was seen to significantly reduce the voiding level in subsequent thermal aging. For several void-prone Cu foils, the anneal led to significant pore formation inside the Cu. In the mean time, Cu grain growth in the void-prone foils showed impeded grain boundary mobility. Such behaviors suggested that the root cause for voiding is organic impurities incorporated in the Cu during electroplating, rather than the Kirkendall effect.

Ultrafast science—the study of highly complex and extremely short-lived transient events—has become an area of significant interest in the materials sciences, physics, chemistry, and biology. This article focuses on the state-of-the-art instrumentation and a few of the available probes and techniques, and intends to give a brief overview of the possibilities and challenges for ultrafast materials sciences and for the instrumentation that is required. The pulsed laser-material interactions are briefly introduced, since they are the principal methods to access and trigger ultrafast processes in materials. The associated time and length scales and a few experimental possibilities in the materials sciences are discussed in the first part of this article. The second part deals with the two most applicable types of pulsed probes, x-rays and electrons, and the associated methods to interrogate ultrafast processes. Emphasis is on their differences, capabilities, and limitations.

The impact of contact materials on the performance of nanostructured devices is expected to be significant. This is especially true since size scaling can increase the contact resistance and induce many unseen phenomenon and reactions that greatly impact device performance. Nanowire and nanoelectromechanical switches are two emerging nanoelectronic devices. Nanowires provide a unique opportunity to control the property of a material at an ultra-scaled dimension, whereas a nanoelectromechanical switch presents zero power consumption in its off state, as it is physically detached from the sensor anode. In this article, we specifically discuss contact material issues related to nanowire devices and nanoelectromechanical switches.

In this article, we review current research activities in contact material development for electronic and nanoelectronic devices. A fundamental issue in contact materials research is to understand and control interfacial reactions and phenomena that modify the expected device performance. These reactions have become more challenging and more difficult to control as new materials have been introduced and as device sizes have entered the deep nanoscale. To provide an overview of this field of inquiry, this issue of MRS Bulletin includes articles on gate and contact materials for Si-based devices, junction contact materials for Si-based devices, and contact materials for alternate channel substrates (Ge and III–V), nanodevices.

Research on contact materials in silicon semiconductor devices has recently gained significant momentum due to the increasing performance demands as the complementary metal oxide semiconductor technology advances. Applications include transistor materials such as gate electrodes and contacts to highly doped semiconductors substrates. This review will discuss the key issues in the development of metal gate electrodes with high-κ dielectrics to replace the conventional polycrystalline silicon electrode. Challenges in establishing a work function measurement technique, the role of the metal/high-κ interface in modulating the effective work function, and a review of leading industry solutions will be discussed.

A novel contact technique to reduce the effective Schottky barrier height on Ge and III–V high mobility semiconductors is described. Single metals are used in combination with an ultrathin dielectric to tune the metal/semiconductor barrier height toward zero by shifting or suppressing the strong Fermi-level pinning. Barrier height reduction in the metal-insulator-semiconductor (MIS) contact structure is verified through direct measurements and deduced from increased diode current and reduced contact resistance. Current demonstrations of the MIS contact have barriers as low as 0.05 eV for Er/SiN/n-Ge and 0.18 eV for Al/Al2O3/n-GaAs. The underlying physics is discussed along with the dependence of the minimum achievable contact resistance and barrier height on the metal, dielectric material, dielectric thickness, and substrate doping. For Ge, the MIS contact provides a possible solution to the low n-type Ge dopant solubility problem and allows for the fabrication of Schottky barrier field-effect transistors. For III–V semiconductors, the MIS contact allows for the use of a non-alloyed contact that is crucial for the scalability of III–V metal oxide semiconductor field-effect transistors.

Effective schemes to address contact resistance between silicide and a highly doped diffused junction are examined. Some of the techniques introduced include (1) metal work function tuning, (2) interfacial dipole engineering, and (3) phase modulation of the nickel silicide. These techniques allow modulation of the Schottky barrier of NiSi to n-Si to less than 0.3 eV, which is crucial to achieve sub 10−8 Ω cm2 contact resistivity for the sub-32 nm technology node.