In the silicon complementary metal-oxide–semiconductor (CMOS) process discussed in Chapter 2, the “back-end” (wiring) portion of the process flow was described (see Figure 11.1(a)) with tungsten (W) vias, two layers of Cu wiring and two layers of deposited dielectric. In the discussion in Chapter 2, perhaps an inkling of the actual complexity of this part of the process was given through the brief discussion of TiN or TaN barrier/adhesion layers, chemical vapor deposition (CVD) of tungsten, chemical–mechanical polishing (CMP) to planarize the W layer, deposition of a copper (Cu) seed layer, followed by a thicker electroplated Cu layer, and a “dual damascene” lithography and etching process to pattern the Cu layers. An actual image of a similar back-end silicon CMOS structure is also shown in Figure 11.1(b).

The interface between a semiconductor and an insulator often determines the viability of the material combination in device structures. Silicon is unique in nature, at least among the semiconductors, for having a robust, reliable oxide that can be grown on its surface. The interface between Si and SiO2 is perhaps the most carefully studied of all material interfaces, and is probably the principal reason why silicon has been the dominant semiconductor material. The fact is that silicon naturally oxidizes in the sense that it can be simply placed in a furnace at high temperature with oxygen or water vapor and one obtains a nice, stable dielectric material that is essentially electrically perfect. This distinguishes silicon from all the other simple column IV semiconductor materials. Germanium can be oxidized, but its oxide is soluble in water, which makes it very hard to do any sort of chemical processing.

Lithography is arguably the most important process step in modern integrated circuit (IC) manufacturing. The ability to print patterns with features as small as 10–20 nm and to place those patterns on a substrate with a precision of a few nanometers is what makes today’s chips possible. Virtually all ICs are manufactured today with deep-ultraviolet (DUV) optical lithography operating with 193 nm photons, the basic process introduced in Figure 1.7.

Silicon integrated circuits (ICs) are pervasive in our world, and the global semiconductor industry today exceeds $500 billion in annual sales. The devices and chips this industry produces support global industries, including consumer electronics, transportation, avionics and many others, that collectively represent a major part of global markets. Devices and chips built with other semiconductor materials such as GaAs, SiC and GaN provide critical components for specific application areas, including high-frequency communications systems, solid-state lighting and power management. It is not incorrect to say that the technical foundation of our modern world is based on semiconductors. The critical role that chips play has led to global competition to design, fabricate and build into advanced systems these remarkable components. Their importance to our world is unlikely to change in the foreseeable future.

In this chapter, we discuss the fabrication of a modern complementary metal-oxide–semiconductor (CMOS) integrated circuit using the individual process steps that are combined in a complete process flow sequence to make the chips. Such an ordered process flow from the sandbox of tools available in different combinations would be used to make any kind of device, such as a biosensor, a microfluidic device or a micro-electromechanical systems (MEMS) device. The wafer’s past history and the future process steps can greatly influence how one chooses to order the individual steps. For example, high-temperature steps at the end of a process could disturb delicate doping profiles introduced early in the process. For this reason, we believe it is worth understanding the choices made in assembling a modern CMOS process flow. Seeing the “big picture” of a complete process flow should also help to put the individual process steps we discuss in subsequent chapters into perspective.

One of the main challenges in designing a front-end process for building a device is accurate control of the placement of the active doping regions. Understanding and controlling diffusion and annealing behavior are essential to obtaining the desired electrical characteristics. Consider a cross-section of a state-of-the-art MOS transistor and imagine what happens when it gets scaled down to smaller dimensions (Figure 7.1). In “ideal” or Dennard scaling, as described in Chapter 1, everything shrinks down linearly from one generation to the next. This means that not only do the lateral dimensions scale, but the vertical dimensions, such as the deep source/drain contacting junctions and the shallower tip or extension junctions, also scale. This maintains the same electric field patterns (assuming the operating voltage also scales proportionally). With the same ℰ-field patterns, the device operates in the same manner as before, except that the shorter channel length allows for faster switching speeds [1].