A series of MnOx –CeO2 binary oxide catalysts were synthesized by polyvinylpyrrolidone -assisted supercritical antisolvent precipitation and the effects of the manganese (Mn)/cerium (Ce) molar ratio and calcination temperature on the structure and properties of MnOx –CeO2 were investigated. A solid solution was obtained at each experimental condition and the highest surface area of 107.6 m2/g was obtained at the Mn/Ce molar ratio of 3:5 and the calcination temperature of 400 °C. Low-temperature selective catalytic reduction of emissions of nitrogen oxides, namely NO, NO2, and N2O (deNOx ) with ammonia (NH3) to convert them into nitrogen and water, was used as model reaction to evaluate MnOx –CeO2 catalytic performance. It is found that the activity first increased and then decreased with increasing Mn content and decreased with increasing calcination temperature. The highest catalytic activity (93.3% NO conversion and 100% N2 selectivity) was obtained at the Mn/Ce molar ratio of 1/1 and the calcination temperature of 400 °C, which was attributed to the combination of high surface area and high redox performance of the catalyst.

As Si-transistor technology advances beyond the 10 nm node, the device research community is increasingly looking into the possibility of replacing Si with novel, high mobility materials as the transistor channel. Among several possible candidate materials, germanium and germanium-tin alloys (GeSn) have emerged as strong contenders for the next generation of complementary metal oxide semiconductor (CMOS) transistors. This article presents a comprehensive overview of the state of the art in Ge and GeSn transistor research. We address several key material challenges involved in fabricating high-performance Ge/GeSn-based CMOS transistors, such as gate stack formation and achieving low-resistance contacts to transistor source/drain regions. Using Ge/GeSn as channel materials, we present a FinFET-based, Si-compatible CMOS solution for device dimensions expected in the 7 nm technology node, discuss the practical challenges involved in realizing this design, and highlight directions for future research.

Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic device roadmap to further improve future performance increases of integrated circuits is required to propel the electronics industry. Attention is turning to III–V compound semiconductors that are well positioned to replace silicon as the base material in logic switching devices. Their outstanding electron transport properties and the possibility to tune heterostructures provide tremendous opportunities to engineer novel nanometer-scale logic transistors. The scaling constraints require an evolution from planar III–V metal oxide semiconductor field-effect transistors (MOSFETs) toward transistor channels with a three-dimensional structure, such as nanowire FETs, to achieve future performance needs for complementary metal oxide semiconductor (CMOS) nodes beyond 10 nm. Further device innovations are required to increase energy efficiency. This could be addressed by tunnel FETs (TFETs), which rely on interband tunneling and thus require advanced III–V heterostructures for optimized performance. This article describes the challenges and recent progress toward the development of III–V MOSFETs and heterostructure TFETs—from planar to nanowire devices—integrated on a silicon platform to make these technologies suitable for future CMOS applications.

Single-wall carbon nanotubes (CNTs) were discovered in 1993 and have been an area of intense research since then. They offer the right dimensions to explore material science and physical chemistry at the nanoscale and are the perfect system to study low-dimensional physics and transport. In the past decade, more attention has been shifted toward making use of this unique nanomaterial in real-world applications. In this article, we focus on potential applications of CNTs in the high-performance logic computing area—the main component of the semiconductor industry. We discuss the key challenges for nanotubes to replace silicon in integrated circuits and review progress made in recent years on the material, device, and circuit integration development of CNT technology.

The implication of shape control in nanocrystal synthesis goes far beyond aesthetic appeal. For metal nanocrystals, the shape not only determines their physicochemical properties but also their technological relevance for catalytic, plasmonic, photonic, and electronic applications. In particular, heterogeneous catalysis is a field that can benefit tremendously from the availability of metal nanocrystals with well-controlled shapes, which may serve to significantly increase reaction efficiency while decreasing material cost. This article provides a brief overview of our recent progress in generating shape-controlled nanocrystals with enhanced catalytic activity toward oxygen reduction and formic acid oxidation, two reactions that are crucial for the successful commercialization of fuel cell technology. The impact on other industrially important reactions will be discussed as well. We hope that this article provides a roadmap for further development of metal nanocrystal-based catalysts with enhanced performance through shape-controlled synthesis.

It is now widely recognized that continued performance gains in electronic computing will require new materials, both in the short and long term. In the short term, the silicon channel in transistors will be replaced by materials with higher mobility that are easier to “scale” (make thinner). In data storage, the goal is to have fast, non-volatile memory with a smaller cell size. In the long term, new architectures and new types of logic devices will be needed in order to further reduce power consumption. New materials cannot only boost performance, but can also add new functionalities, such as on-chip photonics, which can vastly improve interchip interconnects. The need for new materials is a big opportunity for materials research, but also a challenge. Replacement technologies must outperform conventional silicon technology, but also be compatible with the vast infrastructure of silicon manufacturing. Examples of some of the materials advances in the areas of computation, memory, and communication are given in this issue of MRS Bulletin.

The possible use of spin and magnets in place of charge and capacitors, respectively, to store and process information is well known. Magnetic tunnel junctions are being widely investigated and developed for magnetic random access memories. These are two terminal devices that change their resistance based on switchable magnetization of magnetic materials. They utilize the interaction between electron spin and magnets to read information from the magnets and write onto them. Such advances in memory devices could also translate into a new class of logic devices that offer the advantage of nonvolatile and reconfigurable information processing over transistors. Logic devices having a transistor-like gain and directionality could be used to build integrated circuits without the need for transistor-based amplifiers and clocks at every stage. We review device characteristics and basic logic gates that compute with spins and magnets from the mesoscopic to the atomic scale, as well as materials, integration, and fabrication challenges and methods.