Metal properties influencing the transistor threshold voltage

Related to the issue of downscaling in nanoelectronics is the constant need to strike a balance between opposing transistor capacities, where an improvement in one direction gives a deterioration in another. In practice, most performance data are linked together by a web of interdependences. Sections 11.1 and 11.3 exposed such problems for the relationship between channel mobility, capacitive gate coupling and effective EOT. In this chapter we will find an additional problem between the threshold voltage of the MOSFET and drain leakage. In order to achieve circuits with as low power consumption as possible, one needs to decrease the supply voltage for the transistors. This leads to a corresponding decrease in the threshold voltage, which in turn puts demands on the choice of work function values of the materials used as gate metals (Lee et al., 2006).

In traditional CMOS technology, including SiO2 dielectrics, the gate electrode is polycrystalline silicon. An advantage of using this material is that its work function, and thus the threshold voltage of the transistors, can be tuned by doping the polycrystalline material: n-type for n-channel and p-type for p-channel transistors. When efficient capacitive coupling between the gate metal and the transistor channel became an issue, the depletion region occurring at the poly-gate/oxide interface gave rise to a series capacitance, which decreased the coupling to the channel and needed to be eliminated (Engström et al., 2010). This motivated a return to metal electrodes, similar to the situation before the end of the 1970s when the gate metal was aluminum. Due to the need for different work functions of gate metals used for n- and p-channel transistors, new materials were needed. Besides the necessity of increased understanding of how novel dielectrics improve the gate capacitance, this required additional studies of metals for tuning the threshold voltage of transistors.

Motivation for high-mobility channel materials in MOSFETs

The progress of information processing relies on advancements in decreasing the switching time of transistors in logic circuits built on CMOS technology. Defining this quantity as the time it takes to move the transistor between its OFF and ON states, there are two device parameters of specific importance: the sub-threshold voltage swing and the transition time for charge carriers along the channel. The first property, discussed in Chapter 11, depends on the capacitive coupling between gate and channel and is connected with the prospect of realizing high-k gate oxides. As we saw in Section 11.4, the second quality depends on the carrier mobility of the channel material and on extrinsic scattering mechanisms originating from the influence of phonons or charge in the gate oxide or from surface roughness (Laux, 2007). For very short channels, below about 20 nm, additional charge interactions are expected for hot carriers and also between channel charge and carriers in the highly doped source and drain areas (Fischetti et al., 2007; Kuhn, 2011). These limitations have motivated the search for new channel materials with higher intrinsic mobility.

The first steps for such improvements were done by creating strain and compressive stress in silicon to change lattice properties, which modifies the semiconductor band structure and gives rise to lower effective mass and thus higher mobility for electrons in n-channel and holes in p-channel devices, the latter built on Ge/Si compounds (Sugii et al., 1999; Fischetti et al., 2002; Leadley et al., 2010). A more radical encroachment into silicon technology has been the introduction of III–V materials for n-channels to speed up carrier transfer. Not surprisingly, the advantage in one parameter earned by such a modification must be offset by a disadvantage in another. Increased mobility is connected with smaller effective masses, which gives lower density of states in the semiconductor energy bands. InGaAs is an interesting candidate in this connection and, as will be further developed below, this compound requires a larger semiconductor surface potential drop in order to achieve a high enough channel charge for acceptable drive current. Its lower density of states demands a larger gate voltage swing for switching the transistor and gives rise to an inferior sub-threshold slope, thus counteracting the improvement in switching time offered by the larger mobility.

The early days of MOS technology

In the past couple of decades, the increasing influence of electronics on human life has promoted MOS technology to a role of similar significance for cultural change as, for example, electric power transmission and combustion engine transport. The basic device for this development, the metal–oxide–semiconductor field-effect transistor (MOSFET), was patented in 1928 by Lilienfeld. The invention had to wait for realization until 1961 when Khang at Bell Telephone Labs first demonstrated a working device. Until then, one of the main hurdles for implementing Lilienfeld’s idea was finding a material combination such that a surface channel for charge carriers could be brought about by an external electric field. A charge-free surface or interface was needed, which required a structure free of charge carrier traps. Here, silicon technology opened new possibilities. By thermally oxidizing the surface of silicon crystals into SiO2, an insulator was obtained with eminent properties and with a low concentration of traps at the SiO2/Si interface and in its volume. At the beginning of the 1960s, a considerable amount of work was performed to optimize the properties of SiO2 prepared this way and to understand the metal–oxide–semiconductor system. Important contributions to the understanding of the MOS system came from a group of William Shockley’s former disciples at Fairchild Semiconductor in Palo Alto. In the same period, activities were also initiated at the IBM Thomas Watson Research Center, at the Bell labs and at some universities in the USA.

Background

Minimizing the gate oxide charge is a frequent challenge in the development of metal–oxide–semiconductor (MOS) technology. The original procedures were developed at the time when SiO2 was the dominating gate insulator in MOS technology and detailed descriptions of the capture processes involved in these different experimental situations are seldom treated in the literature. Due to the need for device characterization, electrical methods dominate. Few luminescence results have been published, whereas the detailed character of oxide traps has been learnt mainly from electron spin resonance (ESR) data (see Chapters 9–11).

In recent years, especially when electrical methods have been practiced on high-k oxides with interlayers close to the silicon face, the electric field distribution in this environment is more complicated, which increases the complexity of interpreting measured data. In the present chapter, we will expound the charge carrier statistics for oxide traps, the variations in capture mechanisms and the processes between different capture conditions, and analyze their influence on experiments for quantifying capture cross sections of high-k oxide traps. We will mainly study the common techniques for injecting charge into oxide traps by electric fields, using MOS capacitors and transistors. Also, we will peel off a couple of sample dependent properties at some expense of quantitative precision by using two important approximations by (i) assuming that the concentration of electrons available for injection from the semiconductor into the oxide has a constant relation to the effective density of states in the semiconductor conduction band and (ii) neglecting the influence of captured charge on the potential distribution inside the oxide. Furthermore, all reasoning will be limited to electron injection and capture but can readily be turned into corresponding arguments for hole processes.

The motivation for writing this book has grown out of a feeling that a novel, compiled description of more recent results within the MOS area is needed after the often-cited work from 1982, MOS (Metal Oxide Semiconductor) Physics and Technology, by E. H. Nicollian and J. R Brews (New York: John Wiley & Sons). Their work has been of extensive use within the MOS community. However, it only describes silicon dioxide structures and their approach follows a practical engineering path.

In the present text, I have included the most important consequences of using MOS insulators with higher dielectric constants, the so-called high-k oxides. Furthermore, since these insulators have given rise to new challenges from the point of view of materials physics, I have tried to start from a more physical basis. Still, my objective has been to write for a circle of readers including engineers, graduate students and researchers.

The book would not have come about without injections of inspiration from friends and colleagues, who have provided valuable discussion, help and up-to-date research during the preparation and writing of the text. Steve Hall and colleagues at the University of Liverpool, Ivona Mitrovic and Naser Sadeghi together with Henryk Przewlocki at the Institute of Electron Technology in Warsaw, and my former student, Bahman Raeissi, have filled in fuel and criticism for keeping up my typing. Specific and educational discussions on e-mail with Valery Afanas’ev, Douglas Buchanan, Jim Chelikowsky, Paul Hurley, Pat Lenahan, Winfried Mönch, Luca Selmi and Andre Stesmans are highly appreciated. Also, financial backing from the Department of Microtechnology and Nanoscience (MC2) at Chalmers is acknowledged together with the greatly valued assistance from colleagues of MC2 in keeping up my research during the writing period: Dag Winkler, Jan Stake, Peter Modh, Göran Petersson and Fredrik Henriksen.

The concept of tunneling

When changing the gate dielectric material from SiO2 with a dielectric constant εSiO2 to an oxide with higher dielectric constant, k, one can allow for a k/εSiO2 times thicker dielectric and keep the same capacitance as measured from the gate metal. At first glance, a thicker insulator would also be expected to give a lower leakage current. As already touched upon in Section 3.2, additional properties are necessary to fulfill such aspirations. The transmission (tunneling) probability is also strongly dependent on the effective mass of the carrier passing through the oxide and, for a given oxide thickness, on the heights, ΔE, of the energy barriers separating the transistor channel from the gate metal. In choosing a gate oxide with a high dielectric constant as an alternative for SiO2, the first step would be to find a material with high ΔEC and k-values to decrease tunneling. As we will find in this chapter, however, additional properties like image force lowering, traps and the process properties discussed in Chapter 11 also influence the options. Since the quest is to achieve the smallest possible leakage current for a given capacitance, the concept of equivalent oxide thickness (EOT; dEOT) is practical for comparing the leakage currents across different oxides as was demonstrated in Fig. 11.3. Figure 13.1 shows the result of a calculation using the theory to be presented below, where “leakage” is taken as the transmission probability, P, for oxides with different k-values, electron effective masses and barrier heights. Normally, high-k oxides have at least about 50% lower effective masses than SiO2 (Hinkle et al., 2004) and about 50% lower energy offset values (Engström et al., 2007), which decreases the profit of higher k-values as will be discussed in more detail in the following.