The motivation for high-k dielectrics

For each new generation in MOS-technology, a recurrent problem has been the so-called “short channel effect.” It occurs when decreasing the gate length such that the edge of the depletion region at drain approaches the source contact close enough for increasing the leakage between source and drain and for decreasing the transistor threshold voltage (Fig. 11.1(a)). For bulk CMOS technology, the standard method to avoid this issue has been to increase the doping in the channel region in order to decrease the depletion region width of the drain junction. This measure, however, decreases the capacitive coupling between gate and channel and lowers the share of the gate voltage falling across the semiconductor channel. As a consequence, the sub-threshold slope decreases, which in turn slows down the switching speed of the transistor. Furthermore, increased doping levels in the channel give rise to higher scattering probabilities and lowered charge carrier mobility. These problems can be avoided by decreasing the thickness of the gate oxide in order to increase the capacitance between gate and channel such that the oxide capacitance becomes much larger than the channel capacitance and gives a major share of the applied gate voltage to the semiconductor. Measures along these lines were possible until the gate length downscaling reached about 45 nm. At this landmark, the SiO2 dielectric needed to reach a thickness of about 1.5 nm, which gave rise to unacceptable gate leakage levels (Taur et al., 1998; Iwai and Ohmi, 2002; Iwai, 2009; Wong and Iwai, 2006; Frank, 2011).

Engineering efforts at the dawn of MOS technology

In the exploratory phase of MOS technology, a major task was to find a material combination with an insulator/semiconductor interface free of charge. The fortunate coincidence that one of the most abundant elements on earth turned out to be an excellent semiconductor, and that its natural oxide offered an interface of high quality, gave the SiO2/Si structure a pivotal role in the development of electronics during the first 50 years of MOS progress (see Deal, 1974, and references therein). Especially in its role as a gate insulator of MOSFETs, thermally prepared SiO2 was developed to an extremely high electrical quality. The necessary change into a gate insulator with higher dielectric constant, k, to be described in Chapter 11, has not diminished the importance of this material for transistor gate functions. A thin interlayer of around 1 nm of SiO2 or an SiOx sub-oxide most often appears between the high-k material and the silicon interface. This has motivated an ongoing need to understand the physical and chemical properties of silicon dioxide, its sub-oxides, and the oxidation processes occurring at silicon surfaces.

The engineering efforts accomplished in the 1960s quickly found the bearings towards oxides with low enough concentrations of bulk charge and interface states for transistor production. The most widely used electrical methods, C–V (Grove et al., 1964, 1965) and the conductance method (Nicollian and Goetzberger, 1967), described in Chapters 2 and 6, for characterizing interface states and oxide charge, were developed in this empirical period. Also, a comprehensive amount of experimental efforts to find applicable oxidation techniques were undertaken and the most important correlations between oxide quality and process data were found and understood (Deal, 1974). Likewise, a useful phenomenological model for the oxidation process was established (Deal et al., 1965) and the sources of charge creation were identified as the four different classes described in Chapter 2. A more distinct understanding based on first-principle results became possible only later, however, after increased computing power and improved microscopy became available.

High-k oxides with properties interesting for gate stacks

In order to satisfy the demands for lower power consumption in modern transistor design, research focus moved from gate oxides of SiO2 to oxides based on metals from the transition and rare-earth series of the periodic table. The elements of major interest for the purpose are marked with dotted frames in the periodic table, shown in Fig. 3.1. The transition metals, Sc, Ti, Y, Zr, La, Hf and Ta, belonging to periods 4, 5 and 6, all have outer electron shell populated as d-orbitals. The rare-earth metals, starting at Ce and ending at Lu, arise as one of the irregularities in the design of the elements as given by Nature (Grimes and Grimes, 1998; Xue et al., 2000). They are inserted as exceptions between La and Hf. Because of the complicated energy scheme occurring when adding the second d-electron in period 6, 14 f-electrons with lower energy levels are added to provide the rare-earth metals, before the 72nd electron is added as a d-orbital to produce Hf. When reacting with oxygen, these metals give rise to insulators with high dielectric constants, which to some degree are related to their higher ionicity, but also to their atomic structures (Busani and Devine, 2005; Perevalov et al., 2007). This, in turn, links to their electronic configurations. The ionicity concept (Phillips, 1968; Van Vechten, 1969), which measures the degree of electron displacement in a chemical compound, is related to the difference in electronegativity between the reacting atoms as further discussed in Sections 3.2, 3.5 and 3.6 and will be shown to have an important meaning for the dielectric constant and the energy offset values at oxide/silicon interfaces (Engström et al., 2007).

The influence of interface states

The ideal MOS structure as described in Chapter 2 was considered as a pure capacitive system, which means that no internal delay times were involved in the charging quantities as influenced by external electrical perturbation. At the interface between gate insulator and semiconductor, an amorphous material is in intimate contact with a crystal. This gives rise to a certain atomic disorder, which creates electron states of type a as described earlier in relation to Fig. 2.1. Such states communicate with charge carriers in the energy bands of the semiconductor as depicted in Fig. 4.1. For a system including these charge carrier traps, one has to take into account their charging and discharging processes. This gives rise to decay times and an additional capacitance component for the system admittance which is important for the electrical function of the MOS system.

Dealing with a large number of electrons and holes embedded in a “temperature bath” set up by the semiconductor crystal, the method to quantify such influence is by using reasoning from statistical thermodynamics. For this purpose, we first take a general approach in Sections 4.2–4.4 to quantify the probabilities for particles in isolated systems occupying energy states given by the potentials determining their quantization. This will lead us to formulate the dynamics of charge carrier traffic at traps in Section 4.6 and then to expressions for the admittance of MOS systems with interface states in Chapter 6. Since measurements are usually performed on sample volumes with macro-dimensions, the energy quantities obtained need to be considered as thermodynamic quantities. Heat stored by local phonons will be discussed and demonstrated to influence the interpretation of energy quantities, depending on the measurement technique used. At the end of the chapter, we will study the statistics of single traps to find out how such systems can be treated in the same thermodynamic language as trap ensembles.

Thermally stimulated current method

Basic principle

The measurement method of thermally stimulated current (TSC) has a long history in the investigation of interface states and oxide traps (Simmons and Taylor, 1972; Mar and Simmons, 1975) even if it has not reached the same level of attention as the C–V and conductance techniques. It is especially suited for traps positioned close to the oxide/semiconductor interface, often called border traps (Fleetwood et al., 1998). The principle is based on releasing charge carriers from the trap potentials by first cooling the sample to a temperature low enough to make the thermal emission rate of the captured carrier in the region of hours, or long enough to be considered “frozen in.” This is followed by a linear temperature increase, releasing charge carriers, which gives rise to a current from which activation energies and capture cross sections can be obtained.

We will discuss TSC based on an example shown in Fig. 7.1 for a MOS structure with high-k oxide, including interface states and border traps. In our example, the latter are assumed to exist in the transition region, often occurring at the interface between the high-k oxide and an interlayer with properties as discussed in Section 4.5 (Lukovsky and Phillips, 2005).

Internal photoemission

Basic principles

Internal photoemission (IPE) measures the electric current generated by the optical excitation of charge carriers to energies exceeding an energy barrier in order to find the lowest photon energy needed for the process. This energy corresponds to the energy offset limiting carrier escape. Together with X-ray photon spectroscopy (XPS), described in Section 8.2, IPE has become an important method for the experimental determination of energy barrier heights in MOS systems (Afanas’ev and Stesmans, 2007; Afanas’ev, 2008).

The energy scales for thermal processes, discussed in earlier chapters, are to be considered as averages across particle ensembles motivating the introduction of thermodynamic concepts, for example Gibbs free energy, denoted G. Optical excitations, which are the basis of photoemission processes, take place between photons and specific eigenstates. Therefore, the energy quantities may differ from those of thermal processes and will be denoted E in this chapter.

The first theoretical treatment of this physical effect was developed by Fowler (1931) for the escape of electrons from a metal into vacuum. The method has been commonly used for establishing the work functions of metals and the heights of Schottky barriers, using various levels of complexity for the interpretation of measured data (Williams, 1970; Dalal, 1971; Engström et al., 1986). In a MOS structure, the alignments between energy bands of the oxide and the semiconductor and between the metal and the oxide can be measured using the same principle.

Energy band diagram

An MOS system involves a Schottky barrier between a metal and an insulator, and a heterojunction between the insulator and a semiconductor. The energy band diagram of such a combination is shown in Fig. 2.1. One important feature of the structure is the voltage partition between these different components. When a voltage is applied, part of it falls across the insulator and part is taken up in the semiconductor depending on differences in dielectric constants, oxide thickness and charge distributions in the oxide and in the semiconductor. As mentioned in Chapter 1, this voltage division is important for the function of a MOSFET, where the structure in Fig. 2.1 represents the gate. The requirement is that the applied gate voltage, VG, should be transferred as effectively as possible to the semiconductor in order to create efficient band bending for opening a conducting channel in the silicon.

The imperfections of the insulator and of both interfaces give rise to charge carrier traps that become sources of charge and influence the potential distribution. The energy distance, ΦB, between the metal Fermi level, μM in Fig. 2.1, and the conduction band of the insulator depends on the difference in work functions between the two materials, but also on dipole charges created at that interface, as will be further discussed in Chapters 3 and 12. Connected with the insulator and the insulator/semiconductor interface, the origins of charge carrier traps are traditionally divided into four different classes, a–d, as shown in the figure (Deal, 1980). Class a are energy states occurring at energy levels within the interval defined by the energy bandgap of the semiconductor. Due to their physical position close to the semiconductor, they interact with free charge carriers in the semiconductor energy bands. For silicon at room temperature, they adopt thermal equilibrium with the semiconductor with decay times in the range of nano- to milliseconds depending on their positions in the bandgap. They are found to have energy levels tightly distributed across the whole bandgap and are treated as quasi-continuous distributions, Dit, when modeling the interface. Furthermore, they appear as donors as well as acceptors with charge states that are positive or neutral, respectively, for energies above the semiconductor Fermi level, μ, and neutral or negative, respectively, for energies below μ.

Electron spin resonance

Basic principles

When a degenerate electronic energy level is exposed to perturbation by, for example, magnetic or electric fields, the degeneracy is removed and the level is split. Applying a magnetic field on atoms, a fine structure is found among their electron energy levels revealing this phenomenon and known as the Zeemann effect. A corresponding influence from an electric field exists and is labeled the Stark effect. Atomic orbitals are degenerate when populated by two electrons with opposite spin directions with quantum numbers +1/2 and –1/2, respectively. A magnetic field will align the magnetic moments resulting from the two spin directions into a parallel and antiparallel constellation. This gives rise to magnetic moments in opposite directions which makes the electron with positive spin increase its energy, while the negative spin lowers the energy of the other electron. By thermodynamic reasons when removing one of these electrons, the one left will adjust its spin to preferably occupy the lower of the two energy levels. It gives a possibility to study the system through excitations by photons and measure the absorption of photon intensity when exciting the single electron from the lower to the higher level. This is the physical base for spectroscopy by electron spin resonance (ESR). Since a material with single electron spins exhibits paramagnetic behavior, the technique is also labeled electron paramagnetic resonance (EPR). The two names are equally common in literature for designating the same characterization method (Poindexter and Caplan, 1983; Stesmans, 1993; Lenahan and Conley, 1998).

Capacitance contribution from interface states

Interface states will give rise to a capacitance adding to that associated with the semiconductor of the MOS combination. The reason is the charge exchange taking place between captured carriers at the interface and the semiconductor energy bands. Since the emission and capture at the interface states take place by thermal processes, determined by the emission rates, en, and the capture rates, cn = vthσn, with the corresponding quantities for holes, a certain time delay occurs before the capacitance reaches a value given by thermal equilibrium in the semiconductor. As will be demonstrated in this chapter, these events can be used to determine capture properties and energy distribution functions, Dit(ΔG), for electrons and holes, where ΔG is the free energy distance between one of the bands and the interface trap level (ΔGn for electrons and ΔGp for holes).

We consider a conduction band diagram for a MOS interface with an n-type semiconductor biased into weak accumulation, such that a downward bending and an accumulation of electrons takes place at the interface, as shown in Fig. 6.1(a). A weak AC voltage (about 10–20 mV) is added to the DC giving rise to the band bending. The occupation of interface states at thermal equilibrium is determined by the position of the Fermi level, μ, in the semiconductor bulk. An interface state, positioned at energy level GT = μ, will be occupied with a probability of ½ as described by Eq. (4.41).