To save content items to your account,
please confirm that you agree to abide by our usage policies.
If this is the first time you use this feature, you will be asked to authorise Cambridge Core to connect with your account.
Find out more about saving content to .
To save content items to your Kindle, first ensure no-reply@cambridge.org
is added to your Approved Personal Document E-mail List under your Personal Document Settings
on the Manage Your Content and Devices page of your Amazon account. Then enter the ‘name’ part
of your Kindle email address below.
Find out more about saving to your Kindle.
Note you can select to save to either the @free.kindle.com or @kindle.com variations.
‘@free.kindle.com’ emails are free but can only be saved to your device when it is connected to wi-fi.
‘@kindle.com’ emails can be delivered even when you are not connected to wi-fi, but note that service fees apply.
A dual scaling of the turbulent longitudinal velocity structure function $\overline {{(\delta u)}^n}$, i.e. a scaling based on the Kolmogorov scales ($u_K$, $\eta$) and another based on ($u'$, $L$) representative of the large scale motion, is examined in the context of both the Kármán–Howarth equation and experimental grid turbulence data over a significant range of the Taylor microscale Reynolds number $Re_\lambda$. As $Re_\lambda$ increases, the scaling based on ($u'$, $L$) extends to increasingly smaller values of $r/L$ while the scaling based on ($u_K$, $\eta$) extends to increasingly larger values of $r/\eta$. The implication is that both scalings should eventually overlap in the so-called inertial range as $Re_\lambda$ continues to increase, thus leading to a power-law relation $\overline {{(\delta u)}^n} \sim r^{n/3}$ when the inertial range is rigorously established. The latter is likely to occur only when $Re_\lambda \to \infty$. The use of an empirical model for $\overline {{(\delta u)}^n}$, which complies with $\overline {{(\delta u)}^n} \sim r^{n/3}$ as $Re_\lambda \to \infty$, shows that the finite Reynolds number effect may differ between even- and odd-orders of $\overline {{(\delta u)}^n}$. This suggests that different values of $Re_\lambda$ may be required between even and odd values of $n$ for compliance with $\overline {{(\delta u)}^n} \sim r^{n/3}$. The model describes adequately the dependence on $Re_\lambda$ of the available experimental data for $\overline {{(\delta u)}^n}$ and supports indirectly the extrapolation of these data to infinitely large $Re_\lambda$.
In the silicon complementary metal-oxide–semiconductor (CMOS) process discussed in Chapter 2, the “back-end” (wiring) portion of the process flow was described (see Figure 11.1(a)) with tungsten (W) vias, two layers of Cu wiring and two layers of deposited dielectric. In the discussion in Chapter 2, perhaps an inkling of the actual complexity of this part of the process was given through the brief discussion of TiN or TaN barrier/adhesion layers, chemical vapor deposition (CVD) of tungsten, chemical–mechanical polishing (CMP) to planarize the W layer, deposition of a copper (Cu) seed layer, followed by a thicker electroplated Cu layer, and a “dual damascene” lithography and etching process to pattern the Cu layers. An actual image of a similar back-end silicon CMOS structure is also shown in Figure 11.1(b).
The present study focuses on two-dimensional direct numerical simulations of shallow-water breaking waves, specifically those generated by a wave plate at constant water depths. The primary objective is to quantitatively analyse the dynamics, kinematics and energy dissipation associated with wave breaking. The numerical results exhibit good agreement with experimental data in terms of free-surface profiles during wave breaking. A parametric study was conducted to examine the influence of various wave properties and initial conditions on breaking characteristics. According to research on the Bond number ($Bo$, the ratio of gravitational to surface tension forces), an increased surface tension leads to the formation of more prominent parasitic capillaries at the forwards face of the wave profile and a thicker plunging jet, which causes a delayed breaking time and is tightly correlated with the main cavity size. A close relationship between wave statistics and the initial conditions of the wave plate is discovered, allowing for the classification of breaker types based on the ratio of wave height to water depth, $H/d$. Moreover, an analysis based on inertial scaling arguments reveals that the energy dissipation rate due to breaking can be linked to the local geometry of the breaking crest $H_b/d$, and exhibits a threshold behaviour, where the energy dissipation approaches zero at a critical value of $H_b/d$. An empirical scaling of the breaking parameter is proposed as $b = a(H_b/d - \chi _0)^n$, where $\chi _0 = 0.65$ represents the breaking threshold and $n = 1.5$ is a power law determined through the best fit to the numerical results.
The interface between a semiconductor and an insulator often determines the viability of the material combination in device structures. Silicon is unique in nature, at least among the semiconductors, for having a robust, reliable oxide that can be grown on its surface. The interface between Si and SiO2 is perhaps the most carefully studied of all material interfaces, and is probably the principal reason why silicon has been the dominant semiconductor material. The fact is that silicon naturally oxidizes in the sense that it can be simply placed in a furnace at high temperature with oxygen or water vapor and one obtains a nice, stable dielectric material that is essentially electrically perfect. This distinguishes silicon from all the other simple column IV semiconductor materials. Germanium can be oxidized, but its oxide is soluble in water, which makes it very hard to do any sort of chemical processing.
Lithography is arguably the most important process step in modern integrated circuit (IC) manufacturing. The ability to print patterns with features as small as 10–20 nm and to place those patterns on a substrate with a precision of a few nanometers is what makes today’s chips possible. Virtually all ICs are manufactured today with deep-ultraviolet (DUV) optical lithography operating with 193 nm photons, the basic process introduced in Figure 1.7.