The mobile revolution has enabled broad applications with a faster response, small form factors, and more data bandwidth, sensing, and processing power. The industry is pursuing three-dimensional (3D) stacked integrated circuits (ICs) in order to provide higher density interconnects between chips and/or functional blocks, which translates to enhanced system performance. These value propositions are attractive, especially for wireless applications, and will likely lead to further growth of this sector. Recent progress has been reported for development of IC stacking technologies, specifically for wireless applications. However, for full high volume deployment of 3D stacked ICs, a number of technical challenges remain, including many opportunities to be addressed by material enhancements. This article reviews the state-of-the-art technology solutions used for 3D IC stacking and highlights the material properties and remaining technology challenges required to meet the demanding specifications for high volume manufacturing of consumer devices. In particular, it focuses on the electrical (dielectrics and metallic) properties of the interconnects, the thermal and mechanical properties of the integrated components, and the ultimate component level/board level reliability characteristics.

An ecofriendly synthesis is established to obtain ultra-small SnO2 nanoparticles (NPs) doped with metals by a hydrothermal method using only tin tetrachloride, urea, and water as reagents. This synthesis was done in a short period time at low temperature and without surfactants. Microscopy analysis revealed the formation of doped tin oxide NPs with a diameter smaller than 2.8 nm. Un-doped and doped tin oxides were obtained with a tetragonal type rutile structure with an average surface area of 348 m2/g.

The field of electronics packaging is undergoing a significant transition to accommodate the slowing down of lithographically driven semiconductor scaling. Three-dimensional (3D) integration is an important component of this transition and promises to revolutionize the way chips are assembled and interconnected in a subsystem. In this article, we develop the key attributes of 3D integration, the enablers and the challenges that need to be overcome before widespread acceptance by industry. While we are already seeing the proliferation of applications in the memory subsystem, the best is yet to come with the heterogeneous integration of a diverse set of technologies, the mixing of lithographic nodes and an economic argument for its implementation based on overall system function, and cost rather than a narrow component-based analysis. Finally, an extension to monolithic 3D integration promises even further benefits.

To overcome various concerns due to scaling-down device size in future large-scale integration (LSI), it is indispensable to introduce a new concept of heterogeneous three-dimensional (3D) integration in which various kinds of device chips with different sizes, devices, and materials are vertically stacked. To achieve such heterogeneous 3D integration, the key technology of self-assembly and electrostatic (SAE) bonding has been developed. The heterogeneous 3D integration technology with the SAE bonding method has enabled 3D heterogeneous stacking of different types of chips such as the compound semiconductor device chip, photonic device chip, and spintronic device chip on complementary metal oxide semiconductor chips. A 3D image sensor with extremely fast processing speed and a 3D microprocessor with a self-test and self-repair function for future automatic driving vehicles are typical examples of heterogeneous 3D LSIs which we fabricated by the SAE bonding method.

Described is a simple one-pot route for the synthesis of hierarchically porous carbon supported palladium (Pd/C) monoliths with a three-dimensional pore network via self-assembly under basic conditions of a resol polymer. Textural and morphological characterization of the Pd/C monoliths was carried out using nitrogen sorption analysis and scanning electron microscope. Formation of Pd nanoparticles ranging from 35 to 60 nm was observed. Evaluation of catalytic activity for styrene hydrogenation was performed using the Pd/C material as heterogeneous catalyst in batch mode. Studies revealed that the monoliths showed leaching and catalytic activity similar to a commercial Pd/C catalyst.

Solution-processed hole contact layers (HCLs) of metal oxide nanoparticle (NP) films improve performance of organic photovoltaics (OPVs), but have thus far required harsh post-deposition thermal or plasma treatments. Here, we describe a general method to synthesize suspensions of ultrasmall (1–2 nm) MoO3, WO3, NiOx, and CoOx NPs in n-butanol. Spin-coated metal oxide NP films with no post-deposition treatment exhibit high work function and ionization energy consistent with the oxidation states of the metal cations. Metal oxide NP HCLs demonstrate performance matching those of reference conventional and inverted OPVs containing PEDOT:PSS and evaporated MoO3.