Book contents
- Parallel Computer Organization and Design
- Parallel Computer Organization and Design
- Copyright page
- Contents
- Preface
- Commemoration
- Acknowledgments
- 1 Introduction
- 2 Processor Microarchitecture
- 3 Memory Hierarchies
- 4 Multiprocessor Systems
- 5 Coherence, Synchronization, and Memory Consistency
- 6 Chip Multiprocessors
- 7 Quantitative Evaluations
- 8 Graphics Processing Units
- Book part
- Index
2 - Processor Microarchitecture
Published online by Cambridge University Press: 17 January 2026
Book contents
- Parallel Computer Organization and Design
- Parallel Computer Organization and Design
- Copyright page
- Contents
- Preface
- Commemoration
- Acknowledgments
- 1 Introduction
- 2 Processor Microarchitecture
- 3 Memory Hierarchies
- 4 Multiprocessor Systems
- 5 Coherence, Synchronization, and Memory Consistency
- 6 Chip Multiprocessors
- 7 Quantitative Evaluations
- 8 Graphics Processing Units
- Book part
- Index
Summary
The instruction set is the interface between the hardware and the software and must be followed meticulously when designing a computer. This chapter starts with introducing the instruction set of a computer. A basic instruction set is used throughout the book. This instruction set is broadly inspired by the MIPS instruction set, a rather simple instruction set which is representative of many instruction sets such as ARM and RISC V. We then review how one can support a representative instruction set with the concept of static pipelining. We start with reviewing a simple 5-stage pipeline and all issues involved in avoiding hazards. This simple pipeline is gradually augmented to allow for higher instruction execution rates including out-of-order instruction completion, superpipelining, and superscalar designs.
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- Information
- Parallel Computer Organization and Design , pp. 35 - 154Publisher: Cambridge University PressPrint publication year: 2025
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