The Design of CMOS Radio-Frequency Integrated Circuits

INTRODUCTION

Phase-locked loops (PLLs) have become ubiquitous in modern communications systems because of their remarkable versatility. As one important example, a PLL may be used to generate an output signal whose frequency is a programmable, rational multiple of a fixed input frequency. The output of such frequency synthesizers may be used as the local oscillator signal in superheterodyne transceivers. Phase-locked loops may also be used to perform frequency modulation and demodulation, as well as to regenerate the carrier from an input signal in which the carrier has been suppressed. Their versatility extends to purely digital systems as well, where PLLs are indispensable in skew compensation, clock recovery, and the generation of clock signals.

To understand in detail how PLLs may perform such a vast array of functions, we will need to develop linearized models of these feedback systems. But first, of course, we begin with a little history to put this subject in its proper context.

A SHORT HISTORY OF PLLS

The earliest description of what is now known as a PLL was provided by H. de Bellescize in 1932. This early work offered an alternative architecture for receiving and demodulating AM signals, using the degenerate case of a superheterodyne receiver in which the intermediate frequency is zero. With this choice, there is no image to reject, and all processing downstream of the frequency conversion takes place in the audio range.