Skip to main content Accessibility help
Internet Explorer 11 is being discontinued by Microsoft in August 2021. If you have difficulties viewing the site on Internet Explorer 11 we recommend using a different browser such as Microsoft Edge, Google Chrome, Apple Safari or Mozilla Firefox.

Chapter 5: Delay and power of CMOS circuits

Chapter 5: Delay and power of CMOS circuits

pp. 82-104

Authors

, Stanford University, California, , Google Inc., New York, , University of British Columbia, Vancouver
Resources available Unlock the full potential of this textbook with additional resources. There are Instructor restricted resources available for this textbook. Explore resources
  • Add bookmark
  • Cite
  • Share

Summary

The specification for a digital system typically includes not only its function, but also the delay and power (or energy) of the system. For example, a specification for an adder describes (i) the function, that the output is to be the sum of the two inputs; (ii) the delay, that the output must be valid within 1 ns after the inputs are stable; and (iii) its energy, that each add consumes no more than 2 pJ. In this chapter we shall derive simple methods to estimate the delay and power of CMOS logic circuits.

DELAY OF STATIC CMOS GATES

As illustrated in Figure 5.1, the delay of a logic gate, tp, is the time from when the input of the gate crosses the 50% point between V0 and V1 to when the output of the gate crosses the same point. Specifying delay in this manner allows us to compute the delay of a chain of logic gates by simply summing the delays of the individual gates. For example, in Figure 5.1 the delay from a to c is the sum of the delay of the two gates. The 50% point on the output of the first inverter is also the 50% point on the input of the second inverter.

Because the resistance of the PFET pull-up network may be different than that of the NFET pull-down network, a CMOS gate may have a rising delay that is different from its falling delay. When the two delays differ, we denote the rising delay, the delay from a falling input to a rising output, as tpr and the falling delay as tpf, as shown in Figure 5.1.

We can use the simple switch model derived in Section 4.2 to estimate tpr and tpf by calculating the RCtime constant of the circuit formed by the output resistance of the driving gate and the input capacitance of its load(s).1 Because this time constant depends in equal parts on the driving and receiving gates, we cannot specify the delay of a gate by itself, but only as a function of output load.

About the book

Access options

Review the options below to login to check your access.

Purchase options

eTextbook
US$95.00
Hardback
US$95.00

Have an access code?

To redeem an access code, please log in with your personal login.

If you believe you should have access to this content, please contact your institutional librarian or consult our FAQ page for further information about accessing our content.

Also available to purchase from these educational ebook suppliers