Integrated Circuit Fabrication Science and Technology

In the silicon complementary metal-oxide–semiconductor (CMOS) process discussed in Chapter 2, the “back-end” (wiring) portion of the process flow was described (see Figure 11.1(a)) with tungsten (W) vias, two layers of Cu wiring and two layers of deposited dielectric. In the discussion in Chapter 2, perhaps an inkling of the actual complexity of this part of the process was given through the brief discussion of TiN or TaN barrier/adhesion layers, chemical vapor deposition (CVD) of tungsten, chemical–mechanical polishing (CMP) to planarize the W layer, deposition of a copper (Cu) seed layer, followed by a thicker electroplated Cu layer, and a “dual damascene” lithography and etching process to pattern the Cu layers. An actual image of a similar back-end silicon CMOS structure is also shown in Figure 11.1(b).