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Chapter 24: Basic Concepts for Physical Design

Chapter 24: Basic Concepts for Physical Design

pp. 507-536

Authors

, Indraprastha Institute of Information Technology, Delhi
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Extract

A work of art is an … expression of nature, in miniature … The standard of beauty is the entire circuit of natural forms,—the totality of nature … Nothing is quite beautiful alone: nothing but is beautiful in the whole.

—R. W. Emerson, Nature, Chapter 1, 1836

A physical design process takes a design from the structural level to the physical level. We start with a netlist and finally obtain a layout that describes the location and physical connections of each circuit element in a design. We represent a layout as geometrical patterns required to be fabricated on each layer of the silicon wafer for an integrated circuit (IC).

To appreciate the physical design process, we should be familiar with the properties of various layers in an IC, their organization, and the IC fabrication technology. Additionally, we need to understand the interconnect characteristics and their effects on the circuit parameters, such as delay and signal integrity. In this chapter, we will discuss these concepts that are essential for understanding the physical design tasks described in the following chapters.

INTEGRATED CIRCUIT FABRICATION

The IC fabrication technology strongly impacts physical design by enforcing constraints on the layout and deciding figures of merit such as performance, power, area, and reliability. Therefore, we need to understand the basics of IC fabrication.

We carry out IC fabrication in two distinct sets of processes: front end of the line (FEOL) and back end of the line (BEOL). The set of FEOL processes is responsible for fabricating circuit elements such as resistors, capacitors, diodes, and transistors. The set of BEOL processes is responsible for fabricating interconnection layers over the device layers. FEOL processes precede BEOL processes.

FEOL Processing

The FEOL processing starts with a monocrystalline silicon wafer. The starting wafer is typically a lightly doped p-type material. The resistivity, orientation of the crystal, and flatness of the wafer are critical considerations in choosing a wafer.

During FEOL processing, we dope different regions of a wafer with acceptor or donor materials. Doping with an acceptor creates an excess of holes while doping with a donor creates an excess of electrons. Typically, we use boron/aluminum as acceptors and phosphorous/arsenic as donors.

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