Introduction to VLSI Design Flow

In the earlier chapters, we have discussed various tasks involved in a design flow. The design process culminates in sending the final layout to a foundry for fabrication or design tape-out. However, we do not start with the mass production of a chip immediately. Rather we check the first few samples of the fabricated chip by running actual applications under realistic operating conditions. This task is known as post-silicon validation. If we find problems in post-silicon validation, we need to debug and fix them before moving ahead with the mass production of a chip. In this chapter, we will discuss the basic concepts related to post-silicon validation.

NEED FOR POST-SILICON VALIDATION

During the pre-silicon phase, we perform verification on an abstract design model in a virtual environment using simulation, formal verification, and other techniques described in the earlier chapters. For complex designs and system-on-chips (SoCs), some verification gaps inevitably remain in the pre-silicon phase. Consequently, a fabricated chip can produce an unexpected or wrong response on an actual application. We need to detect such unexpected behavior of the fabricated chip and fix them before it reaches the end-users on a large scale.

Despite tremendous progress in the pre-silicon design verification techniques, we obtain errors in a majority of newly manufactured SoCs [1]. The primary reasons why verification gaps remain in the pre-silicon stage are as follows:

• 1. Inadequate functional coverage: The speed of simulation and other functional verification methods is orders of magnitude slower than obtaining results using a fabricated chip. The increasing complexity of integrated circuits (ICs), the exponential growth in the design space, and the tighter design schedule leave room for undetected functional issues in the pre-silicon stage. In contrast, we can verify the functionality of a fabricated chip by running software, operating systems (OS), and other real-world applications at full speed and for a longer duration, which is not possible using simulation-based verification. For example, we can execute the OS boot sequence on a fabricated chip in a few seconds, while simulating it using a register transfer level (RTL) model will require several years [2]. Hence, post-silicon validation allows us to cover those scenarios and operating conditions in the post-silicon validation stage that were missed during the pre-silicon functional verification.