Introduction to VLSI Design Flow

In a sequential circuit, the controllability and observability of signals are low. The state elements (flip-flops) need to transition through several clock cycles before the value propagates from the input ports to an internal pin. We encounter a similar problem in observing the value of an internal pin at some output port. In the worst case, the number of clock cycles required to read or write a bit onto an internal pin can be exponential in the number of flip-flops. Even in a circuit with only a hundred flip-flops, the number of required clock cycles can make testing infeasible.

There are several problems associated with the low controllability and observability of signals. First, the tester will require a large number of clock cycles in applying the test pattern sequence. It increases the test execution time and the cost of testing. Second, it becomes difficult for the automatic test pattern generation (ATPG) tools to find the sequence of a test pattern for a given fault. The difficulty primarily arises because finding a test pattern in a sequential circuit requires state exploration or searching for the appropriate sequence of states. Since, in general, there can be too many states, finding a test pattern sequence in a sequential circuit becomes challenging. Therefore, the test development time becomes dramatically high for a sequential circuit. Consequently, we might need to sacrifice the fault coverage, and the quality of testing can suffer.

We can tackle the above problems by employing the scan design methodology. In this methodology, we modify the sequential circuit to improve signal controllability and observability. Consequently, test pattern generation and test pattern application by the tester become extremely efficient. In this chapter, we will explain the scan design methodology in detail.

BASICS OF SCAN DESIGN TESTING

The basic principle of a scan design methodology is to make design modifications such that controlling and observing the state of memory elements in a design becomes easier than in the original sequential circuit [1].

Salient features: The salient features of scan design methodology are listed below and illustrated in Figure 21.1.