Introduction to VLSI Design Flow

In the previous chapters, we have discussed various physical design tasks, viz. chip planning, placement, clock tree synthesis, and routing. After performing these tasks, we obtain a layout that contains sufficient information for fabricating a chip. However, we need to perform some post-layout verification tasks on the final layout before sending it to the foundry for fabrication. These verification tasks ensure that the final layout delivers the desired functionality, meets the power, performance, and area (PPA) requirements, adheres to rules provided by the foundry, and is free from signal integrity (SI) issues and other electrical problems. Note that we carry out some of these tasks in the earlier stages of the design flow also. However, now we perform these tasks more rigorously because this is the last opportunity to fix design problems before fabrication. Additionally, the final layout allows us to perform these tasks more accurately because it contains complete design information.

The post-layout verification involves three major tasks:

• 1. Layout extraction: The layout describes the polygons or shapes required on each fabricated layer. We need to extract various information from the layout so that other verification tools can work with the extracted information. The problem for a verification tool is greatly simplified if it works with the extracted information rather than the original layout.

• 2. Physical verification and signoff checks: We need to check whether a layout adheres to manufacturability rules, matches the functionality of the initial netlist, and is free from electrical and timing problems. We refer to the checks that we carry out on the final layout before sending it to a foundry as signoff checks.

• 3. Engineering change order (ECO): If we need to make some minor changes to a design almost at the end of a design flow, we make these changes and carefully verify them using an ECO process.

• In this chapter, we will discuss the above post-layout verification tasks in detail.

LAYOUT EXTRACTION

There are two major steps in layout extraction: circuit extraction and parasitic extraction. The circuit extraction involves extracting devices and their interconnections to reconstruct the circuit that the layout is supposed to represent.