…before attempting to translate our data into the rigorous language of symbols, it is above all things necessary to ascertain the intended import of the words we are using. But this necessity cannot be regarded as an evil by those who value correctness of thought, and regard the right employment of language as both its instrument and its safeguard.
—George Boole, An Investigation of the Laws of Thought, Chapter 4, 1854We model hardware at the register transfer level (RTL) using hardware description languages (HDLs) such as Verilog and VHDL, as discussed in the preceding chapters. Subsequently, we synthesize the RTL model and obtain a netlist. During the initial phases of synthesis, we translate the RTL model to a netlist consisting of primitive logic gates, arithmetic blocks, and memory units, including registers. We refer to this step as RTL synthesis.
RTL synthesis involves analyzing the RTL model and instantiating appropriate circuit elements based on the semantics of the HDL. Therefore, it needs to comprehend various HDL constructs while translating them to circuit elements. In this chapter, we will illustrate the translation of a few essential Verilog constructs to hardware. These examples help us understand the correspondence between the Verilog constructs and the circuit elements. These concepts are often helpful while developing an RTL model, evaluating the impact of RTL code changes on the quality of result (QoR) measures, making manual RTL modifications, and interpreting the results of logic synthesis.
There are some optimization tasks that we can perform more efficiently at the level of RTL model. For example, we can efficiently carry out optimization related to resource allocation, arithmetic operators, multiplexer usage, and finite state machines (FSMs) at RTL because the HDL constructs allow easy identification of targets and make modifications at a higher abstraction level. We will discuss these optimizations also in this chapter.
LOGIC SYNTHESIS TASKS
We divide logic synthesis into a series of smaller tasks, as illustrated in Figure 10.1.
The initial portion of logic synthesis consists of parsing the RTL code, elaboration, RTL-specific optimization, and translation to primitive logic gates, arithmetic blocks, registers, memory units, and FSMs. We group these tasks as RTL synthesis and will discuss them in detail in this chapter.
After RTL synthesis, we carry out aggressive logic optimization, technology mapping, and technology-dependent logic optimizations. These tasks produce the final netlist that we can use for physical design.
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