Introduction to VLSI Design Flow

A critical task in physical design is to determine the locations of each entity in a design. In Chapter 25 (“Chip planning”), we have discussed how we determine the position of larger entities such as macros, memories, analog blocks, and input/output (I/O) pads during floorplanning. However, we also need to decide the locations of numerous standard cells in a design. We make these decisions during placement. The tool that performs placement is referred to as a placer.

The primary goal of placement is to ensure that the design becomes routable. This task is challenging because a placer must decide the cell locations without carrying out actual routing. Typically, placers use cost measures that are easier to compute, such as the total wire length (WL), rather than directly estimate the routability of a design. Intuitively, to reduce WL, a placer should place the connected cells nearby. Therefore, minimizing total WL often improves routability. Moreover, a bad placement solution can make a design unroutable or prevent meeting timing requirements. Hence, other cost measures, such as timing and congestion, are also considered by a placer. The placement methodology that targets improving the slack of the timing paths is known as timing-driven placement and is widely employed for industrial designs.

The placement problem is challenging due to the large number of standard cells that needs to be placed. Placers often need to tackle more than a million cells in an industrial design. We need to consider this aspect of the problem while developing placement strategies.

Typically, we simplify the placement problem by dividing it into multiple tasks: global placement and legalization, followed by detailed placement.

During the early phases of placement, we try to find approximate cell locations and treat cells as point objects [1]. We spread the cells over the layout reducing the cell density and minimizing some cost metrics, such as the total WL. The cell locations are decided just by their connectivity, and we ignore the attributes of a cell, such as its size and pin locations. This task is known as global placement.