…any real body must have extension in four directions: it must have Length, Breadth, Thickness, and—Duration … It is only another way of looking at Time … For instance, here is a portrait of a man at eight years old, another at fifteen, another at seventeen … All these are evidently sections, as it were, Three-Dimensional representations of his Four-Dimensioned being…
—H. G. Wells, The Time Machine, Introduction, 1895In a synchronous circuit, the clock signal synchronizes the operation of various circuit elements. For deterministic circuit operation, certain timing constraints must be satisfied between the data signal relative to the clock signal. If these constraints are violated then the circuit can go into a metastable state or an invalid state. Therefore, we need to verify that these constraints are indeed satisfied in a synchronous circuit [1–4]. We use static timing analysis (STA) for this purpose. The simplicity and computational efficiency of STA have made synchronous design methodology the de facto standard for complicated digital circuits.
An STA tool verifies that a given synchronous circuit operates deterministically and remains in a valid state for a given frequency even in the worst-case scenario. Note that the purpose of STA is not to find a frequency at which a circuit can operate. Its purpose is just to ascertain whether a given circuit can safely operate at a given frequency and operating conditions. Therefore, STA needs to examine only the worst-case behavior for the circuit. It greatly simplifies the problem for an STA tool. It need not evaluate the circuit response to all possible input stimuli because most of them do not contribute to the worst-case behavior. Hence, STA employs methods that do not require applying stimuli and observing their dynamic responses. In this sense, STA is a static verification technique. It employs efficient stimuli-independent techniques to examine the worst-case behavior of a circuit.
In this chapter, we first describe the expected behavior of a synchronous circuit. Then, we derive the timing constraints that must be met to achieve this synchronous behavior. Next, we explain the techniques employed by the STA tools to ensure that these constraints are satisfied. We also highlight the assumptions used by the STA tools and point out the merits and demerits of these assumptions. Finally, we explain some of the popular techniques to account for variations in STA.
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