Introduction to VLSI Design Flow

We can implement a given functionality in various ways. For example, to add two binary numbers, we can implement it using different architectures, employ standard cells of different sizes, place them on the layout in many legitimate ways, and connect them using several alternative routes. These implementations can differ in power, performance, and area (PPA). For example, a carrylookahead adder (CLA) can exhibit better speed than a ripple carry adder, though at the expense of increased area. However, as a designer, we know the target application and the required attributes of the circuit. We define and convey these requirements to electronic design automation (EDA) tools using constructs known as constraints.

During implementation steps, such as logic and physical synthesis, EDA tools attempt to ensure that the constraints are honored. Similarly, verification tools such as the static timing analysis (STA) tool check whether the specified constraints are met, independent of the implementation tool. Thus, constraints act as a common denominator for the implementation and verification tools.

We specify requirements or design constraints using Synopsys Design Constraint (SDC) commands in a set of ASCII files [1]. These files are known as constraint files or SDC files. Note that there can be different constraint files for different modes of operation, such as functional mode, test mode, and scan mode, due to mode-dependent timing requirements.

In this chapter, we will discuss various design constraints and their relevance. We will also demonstrate, using examples, how we can define them in the SDC format. However, note that this chapter does not exhaustively describe the SDC commands and their arguments (options). For an exhaustive list of SDC commands, readers should refer to the SDC user guide or tool-specific manuals. Additionally, it is worth pointing out that EDA tools can also provide some proprietary commands and mechanisms to gather additional information about the design. In this book, we will not discuss tool-specific commands. Readers should refer to them in tool-specific user guides and reference manuals.

Most of the design constraints specified in a constraint file are related to the timing and used during STA. Therefore, a constraint file is also referred to as a timing constraint file. In this chapter, we will explain STA-specific design constraints in detail.