Introduction to VLSI Design Flow

We fabricate ICs using sophisticated technology and under tight process control. Nevertheless, during fabrication, defects can sneak in, and the functionality of the fabricated IC can differ from its design [1]. Therefore, post-fabrication, we should detect defective ICs and prevent them from reaching the end-user. This is the primary purpose of testing an IC.

At the outset, it is important to understand the difference between a verification process and a testing process. A verification process ensures that the functionality of a design meets its corresponding specification. We carry out verification processes multiple times in a design flow to ensure the design correctness. Therefore, verification processes work on design representations such as RTL, netlist, layout, or GDS.

In contrast, we carry out testing on a fabricated IC. The objective of testing is to ensure that the IC has been fabricated as per the given design. Therefore, testing ensures that the functionality of the fabricated IC meets the given design. To achieve this, we need to detect defects introduced during manufacturing.

There are several steps in a design flow that enable or reduce the complexities of test processes. Therefore, even though we conduct testing after fabrication, we can enhance its efficiency and effectiveness by considering testing during the design phase. Consequently, test-related design steps are now an integral part of the VLSI design flow [2].

In this chapter, we introduce the testing techniques. We will explain the details of the testing techniques in Part III of this book.

MANUFACTURING DEFECTS

Origin of Defects

The fabrication of an IC is a complex process. It requires an extremely clean environment and tight process control. In addition to particulate and gaseous contaminants, we need to tightly control factors such as vibration, static electricity, and operational practices. We refer to the tightly controlled environment of IC manufacturing as cleanrooms [3].