Introduction to VLSI Design Flow

We model the behavior of a digital circuit in hardware description languages (HDLs), such as Verilog and VHDL, as described in Chapter 8 (“Modeling hardware using Verilog”). Subsequently, we need to ensure that the logical functionality of the HDL model matches the given specification. This task is accomplished by functional verification. The goal of functional verification is to ensure that the logic implementation of the digital circuit is correct, i.e., it produces the right output bit sequence for a given input bit sequence. We can initially ignore the delay of combinational circuit elements during functional verification or make some simplistic assumptions about them. As more details are added to a design, we perform verification tasks related to delay, power dissipation, and correctness of layout later in the design flow. By segregating functional verification from other types of verification tasks, we are able to simplify the overall design verification process.

We can broadly categorize functional verification techniques into two classes: simulation-based techniques and formal methods. Simulating a hardware model is analogous to running a program written in a traditional programming language and ensuring the correctness of the program by observing its output. Therefore, simulation-based techniques are easy to use and can quickly discover bugs in a hardware model, especially in the early stages of design implementation. In practice, simulation-based techniques provide a foundation for functional verification. Subsequently, we augment and fill gaps in the simulation-based verification with more rigorous formal methods.

In this chapter, we will explain the simulation-based techniques for functional verification. In Chapter 11 (“Formal verification”), we will discuss techniques based on formal methods.

BASICS OF SIMULATION

A typical simulation framework is shown in Figure 9.1. It involves applying stimulus to the design under verification (DUV) and observing its response for correctness. We commonly refer to the verification environment created for applying stimuli and observing responses as a testbench [1]. A testbench interacts with a tool, known as simulator, to produce verification results and debugging information.