…imperfection is in some sort essential to all that we know of life … No human face is exactly the same in its lines on each side, no leaf perfect in its lobes, no branch in its symmetry. All admit irregularity as they imply change … All things are literally better, lovelier, and more beloved for the imperfections …
—John Ruskin, The Stones of Venice, Vol. II, Chapter 6, 1853In a synchronous design, the clock signal orchestrates all its operations. It is responsible for the launch and the capture of data at the flip-flops. During logic synthesis, we assume that an ideal clock signal triggers all the flip-flops. An ideal clock has the same waveform (voltage vs. time relationship) at all the points in the circuit. It implies that, for a given clock signal, all the flip-flops launch and capture data at the same time instant. In other words, there is no clock skew or difference in the arrival time of the clock signal at the launch and the capture flip-flops.
In physical design, the assumption of an ideal clock does not hold. Clock signals are generated by some clock source (either external or internal) and distributed throughout a circuit. When a clock signal propagates through a circuit, it encounters path-dependent delay due to parasitic resistances and capacitances. Therefore, delivering an ideal clock signal to the clocked circuit elements is impossible for practical designs.
Given that we cannot deliver an ideal clock signal physically, clock tree synthesis (CTS) aims to implement a clock distribution network that delivers a clock signal that is similar to an ideal clock. Specifically, CTS aims to minimize the clock skew. To achieve this, CTS employs special routing topologies and circuit elements such as clock buffers to obtain a balanced delay in the clock distribution network. Since clock distribution networks can be responsible for 25–70% of the total dynamic power dissipated in a circuit, CTS also attempts to reduce the clock network's power dissipation [1–3]. Moreover, post-CTS new timing violations can appear due to the nonideal clock behavior. CTS tries to fix these timing violations also.
Traditionally, achieving zero clock skew is the goal of CTS. However, sometimes system performance can be improved by maintaining useful skews on specific clock paths. Therefore, CTS inserts useful skews by building an unbalanced clock network wherever it finds such opportunities.
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