Introduction to VLSI Design Flow

Earlier, we discussed dividing the RTL to GDS implementation flow into two parts: logic synthesis and physical design. In this part of the book, we will discuss logic synthesis. In Part IV, we will discuss physical design.

Logic design involves transforming a high-level functional description to a netlist of standard cells and macros. It takes a design from the functional domain to the structural domain. The primary task of logic design is to decide the logic elements that will deliver the required functionality. Additionally, we need to ensure that the design metrics such as area, performance, power, and testability meet the given requirements.

To ensure that the logic design meets the above requirements, we interleave implementation and verification tasks in a design flow. We have arranged implementation and verification-related chapters similarly. However, note that we carry out some of the verification tasks, such as combinational equivalence checking, timing analysis, and power analysis, multiple times in a design flow.

We will explain implementation of the logical design in Chapter 8 (“Modeling Hardware using Verilog”), Chapter 10 (“RTL Synthesis”), Chapter 12 (“Logic Optimization”), Chapter 16 (“Technology Mapping”), Chapter 17 (“Timing-driven Optimization”), and Chapter 19 (“Powerdriven Optimization”). We will discuss verification aspects for a design in Chapter 9 (“Simulationbased Verification”), Chapter 11 (“Formal Verification”), Chapter 14 (“Static Timing Analysis”), and Chapter 18 (“Power Anlaysis”). We will present the information that is used both in implementation and verification in Chapter 13 (“Library”) and Chapter 15 (“Constraints”).

It is worthy to point out that the primary objective of these chapters is to build a foundation for logic design. Therefore, we explain essential concepts and principles governing it. We have attempted to provide explanations not based on any specific logic synthesis tool or proprietary data format. Therefore, a reader can apply these concepts to any tool s/he chooses for logic design. Additionally, note that these chapters build a foundation for logic design. To gain more depth on these topics, we encourage readers to refer to standard textbooks on them. We have provided references to those textbooks at appropriate places in each chapter.