Introduction to VLSI Design Flow

As described in Chapter 4 (“RTL to GDS implementation flow”), we divide logic synthesis into two distinct phases: technology-independent phase and technology-dependent phase. The first task in technology-dependent phase is to map a netlist of generic gates to the cells of the given set of technology libraries. This task is known as technology mapping, or mapping in short. The tool or the software that carries out technology mapping is referred to as technology mapper, or mapper. Post-mapping we perform further technology-dependent logic optimizations [1, 2].

The attributes of timing, area, and power for cells are defined in a technology library. Therefore, mapping brings a significant transformation to a design by describing the timing, area, and power characteristics of each instance in a design. Consequently, the final quality of result (QoR) of a design depends heavily on the mapping. Moreover, post-mapping, the level of abstraction in a design decreases, and making further changes to the instances of a design becomes difficult. Thus, mapping is one of the most critical tasks of a design flow. We will discuss various aspects of mapping in this chapter.

BASICS OF MAPPING

The application framework of a technology mapper is shown in Figure 16.1. Let us examine its various components.

Inputs: A mapper takes a set of technology libraries, a given design, and constraints as inputs.

• 1. Technology libraries: A technology library consists of cells with different functions. For example, a library can contain cells implementing logic functions such as AND, OR, NOT, multiplexer, flip-flops, and latches. These cells can have a different number of inputs. For example, there can be cells implementing two-input AND gate, three-input AND gate, fourinput AND gate, etc. A mapper can use a combination of smaller gates or an equivalent big gate during mapping.