Introduction to VLSI Design Flow

In the previous chapter, we discussed design implementation: from RTL to the final layout. We carry out design implementation with the help of sophisticated EDA tools. These tools need manual inputs to gather design information, set tool options, and obtain hints to guide their algorithms. As a design gets transformed and moves through various EDA tools and design teams, bugs can creep into it. Some frequent bug sources are human error, miscommunication, inappropriate usage of EDA tools, and unexpected EDA tool behavior. These bugs can make a design erroneous. Therefore, it is critical to detect bugs or design problems using some verification techniques.

If design verification fails, we need to take some remedial actions. Therefore, it is prudent to verify a design as soon as we make some non-trivial design changes so that debugging and fixing effort is minimized. Hence, we need to verify a design multiple times during a design flow. Consequently, during designing, we spend significant effort on verification alone [1–3]. In the future, with the increase in design complexity, the verification effort is expected to increase further.

During various stages of a design flow, we employ different verification techniques. These techniques differ in exhaustiveness, computational resource requirement, and designer effort. In this chapter, we will briefly discuss some of the commonly used verification techniques. We will discuss these techniques in detail in Part II and Part IV of this book.

SIMULATION

During the early stages of a design flow, we represent the functionality of a design using an RTL model. Given a functionality, we can manually develop RTL models, reuse existing RTL, or generate them using a behavioral synthesis tool. Irrespective of the source, we need to verify that the RTL functionality matches the specification. Typically, we employ simulation to verify the functional correctness of an RTL model [4].

Using simulation, we mathematically compute the response of a given design for a given input or stimulus. We specify stimulus by a sequence of bits (0 or 1) at the input ports. We also specify the timing information such as when does 0 → 1 or 1 → 0 transition occur. A set of input stimuli applied to a circuit is commonly referred to as test vectors or test patterns.