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Chapter 18: Power Analysis

Chapter 18: Power Analysis

pp. 401-421

Authors

, Indraprastha Institute of Information Technology, Delhi
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Extract

There are few facts in science more interesting than those which establish a connexion between heat and electricity.

—James Prescott Joule, “On the heat evolved by metallic conductors of electricity, and in the cells of a battery during electrolysis,” The London, Edinburgh, and Dublin Philosophical Magazine and Journal of Science, 1841

The power–performance trade-off has now become a key ingredient in VLSI design flows. The increased power dissipation in integrated circuits (ICs) and the ubiquitous use of battery-powered devices have made incorporating power-saving techniques essential to the design flows. Since powersaving strategies are more effective early in the flow, we adopt low-power design methodologies right from the pre-RTL stages. Subsequently, the power-related tasks permeate throughout the design flow.

We can broadly classify the power-related tasks as: power analysis and power-driven optimizations. In this chapter, we will explain power analysis methods. In the next chapter (“Powerdriven optimization”), we will discuss power optimization techniques.

COMPONENTS OF POWER DISSIPATION

There are two components of power dissipation in a CMOS circuit: dynamic power dissipation and static power dissipation. The dynamic power dissipation occurs when a circuit performs computation actively, i.e., a signal or the output of a logic gate changes its value. The static power dissipation occurs when the circuit is powered on (supply voltages are applied), but it does not perform active computation. Let us understand these components of power dissipation in more detail.

Dynamic Power Dissipation

Consider a CMOS inverter II, shown in Figure 18.1(a). The output pin drives the input of other logic gates through wires. The total load due to these M input pins is CI = ΣM i=1 Ci, where Ci is the capacitance of the ith input pin. The wires offer load capacitance Cw. Additionally, the driving pin Z has parasitic capacitances Cd due to the drain diffusion regions of the transistors. Thus, an output pin of a CMOS logic gate has total load capacitance:

We can use the circuit shown in Figure 18.1(b) for understanding dynamic power dissipation. Assume that the inverter undergoes a transition from 0→1 or 1→0. These transitions lead to power dissipation due to switching of capacitors and due to drawing short-circuit current from the power supply. We discuss these components of power dissipation in the following paragraphs.

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