Introduction to VLSI Design Flow

Obtaining a register transfer level (RTL) model for a design is often the starting point of a design flow. We model RTL using hardware description languages (HDLs), such as Verilog and VHDL. We synthesize an RTL model to obtain a netlist. Subsequently, we use this netlist in the design flow.

In this chapter, we will describe modeling of hardware using Verilog. We will primarily focus on the language constructs and explain their application in creating hardware models. We will describe the impact of Verilog constructs on simulation and synthesis in Chapter 9 (“Simulationbased verification”) and Chapter10 (“RTL synthesis”), respectively.

This chapter is an introduction to Verilog. It will enable readers to understand various constructs in a given Verilog code, develop Verilog models, and subsequently use the Verilog models in a design flow. For a deeper understanding, we advise readers to refer to dedicated resources on Verilog and the IEEE Std 1364-2001 [1–3].

HARDWARE DESCRIPTION LANGUAGES

HDLs are created to describe hardware easily and realistically. They enable designers to express the design intent and functionality in a precise manner. Moreover, they allow electronic design automation (EDA) tools to extract design information and process them efficiently. Therefore, HDLs have several features distinct from conventional programming languages such as FORTRAN, C, and C++. Some of the distinctive features of HDLs are:

• 1. Concurrency: Hardware can compute concurrently. Different components in a circuit such as flip-flops, adders, and multipliers can compute in parallel.

The above example illustrates that we need to describe the sequence of operations in the hardware model. HDLs need to provide features to support both parallel and sequential operations. Additionally, it should enable EDA tools to distinguish between these two types of operations unambiguously.