Introduction to VLSI Design Flow

Before technology mapping, the netlist consists of generic gates. We refer to this netlist as unmapped netlist. After technology mapping, the netlist consists of cells from the technology libraries. We refer to this netlist as mapped netlist.

We have discussed logic optimization of unmapped netlist in Chapter 12 (“Logic optimization”). It primarily minimizes the circuit area. The delay estimates in an unmapped netlist are typically based on logic depth. These delay estimates can differ widely from the delay estimates of the mapped netlist. Therefore, we do not carry out timing-specific logic optimizations on an unmapped netlist.

We can perform static timing analysis (STA) on a mapped netlist using the associated technology libraries and the Synopsys Design Constraint (SDC) files. The timing models of library cells are trustworthy. Therefore, post-mapping STA fairly exposes potential timing issues in a design. Consequently, we can perform timing-driven optimizations on a mapped netlist. By timing-driven optimizations, we refer to design transformations that increase the maximum operable frequency of a circuit or fix timing issues in it.

In this chapter, we will discuss timing-driven optimizations that are performed on a mapped netlist.

MOTIVATION

To improve timing of a mapped netlist, one of the approaches can be to include the gate delays in the cost function within the mapping algorithm and allow the mapper to perform timing-driven optimizations [1–3]. However, this task is challenging, as explained below, and we can often find several opportunities for timing optimizations on the mapped netlist.

Challenges of timing-driven technology mapping: Technology mapping proceeds in two steps: finding matches for an unmapped gate (or vertex in an equivalent graph) and covering it.1 While finding suitable matches for an unmapped gate, we still have unmapped logic gates in its fanout. We do not know the input pin capacitance of the unmapped logic gates. Hence, it is challenging to compute delays of the possible matches because the gate delay depends on its output load. Therefore, we cannot select optimum cells that will be suitable for the future loading condition.